mcg@omepd (Steven McGeady) (04/07/88)
The following is a ***PRESS RELEASE*** distributed by Intel today (4/6).
If anyone thinks that the repetition of press releases in this forum is
inappropriate, please stop reading here and take the matter up with me via
e-mail. On the other hand, I feel this is a service to the net. I have
offered the release with a minimum of editing to remove the more content-free
parts that might most offend the net, and have added some details present
in other distributed materials.
When I have time (probably in about a week), I will post a more detailed
discussion of the 80960 architecture. In the meantime, For detailed
information, please contact your local Intel sales office or the phone
number listed below.
S. McGeady
Intel Corporation
mcg@omepd.intel.com mcg@iwarp.intel.com
tektronix!ogcvax!omepd!mcg intelca!omepd!mcg
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INTEL ANNOUNCES FIRST EMBEDDED CONTROL PRODUCTS AND TOOLS BASED ON NEW
80960 ARCHITECTURE
Chandler, AZ, April 6, 1988 -
Intel Corp. today announced a new 32-bit microprocessor architecture that
integrates RISC design techniques, and is optimized for
high-performance embedded control applications.
The 32-bit core architecture, the 80960, has parallelism and modular
features to enable future processors to have very high performance
levels, beyond those scaled to typical speed increases. The modularity
of the core architecture also provides the basis for Intel to develop
market-specific processors. Applications for these processors include
image-processing, protocol handling and motor control. The 80960
processors' performance start at 7.5 VAX MIPS on a single 32-bit
processor.
"The 80960 architecture has been created specifically to address the
product development requirements of the embedded control marketplace
well into the 1990's," said Dave House, Intel Microprocessor Components
Group senior vice president.
"We have incorporated features that assure continuing growth in
performance, coupled with features that make the 80960 family cost
effective and easy-to-use."
--
The 80960KB and the 80960KA are the first two available processors
based on the core architecture. These embedded processors, based on more
than 350,000 transistors, incorporate specific attributes to meet the
high-performance needs of the system control segment of the embedded
control marketplace. Immediate applications for these two embedded
processors are numerics processing, robotics and high-speed
wide-area telecommunications.
"The 80960 embedded processors provide significant price-performance
advantages over most other single-chip, 32-bit embedded solutions," said
Alan Steinberg, product line marketing manager. "For example, the 80960KB
is the only processor available which integrates an on-chip floating-point
unit - at four MegaWhetstones - with a 20MHz clock. That is more than twice
The performance at one-half the cost of other available processors."
--
The highly-integrated 80960KB has a number of functions on-chip that
are characteristic of multiple-chip solutions. On-chip functions include
32 32-bit registers, the FPU [with four additional 80-bit registers],
a 512-byte instruction cache, a stack frame cache, and a 32-bit multiplexed
burst bus.
[Interrupt controller - 256 programmable vectors]
[IEEE-754 compliant FPU, with single, double, and extended
(80-bit) precision operations.]
[Burst bus can load four words at a time.]
... Every design decision was made toward optimizing overall system costs.
"The market for embedded control applications usually has strict cost points
for end systems. Providing the option to use lower-cost DRAMs is a good
example of how we help designers contain overall costs without sacrificing
performance."
[80960KA is 80960KB without FPU].
--
Intel is providing development tools ... for the new embedded processors
today. The Starter Kit ... contains the EVA-960KB software evaluation
vehicle [a plug-in board for the PC-AT with a 20MHz processor a 1Mb of
SRAM] and the ASM-960 assembler [also the linker, librarian, namelister,
etc, based on familiar UN*X tools]. [This starter kit] is priced at
$6000 ...
[A second] Starter Kit is tuned to embedded control application
benchmarking as well as large, sophisticated code development for the
80960KB. [This kit] also consists of the EVA-960 and ASM-960, plus the
iC960 C language compiler with ANSI extensions [prototypes, const, volatile,
etc]. iC960 also includes a retargetable STDIO library, full 32-, 64-,
and 80-bit IEEE-compatible floating-point library, and in-line assembly
languages [inserts, that fit with quality compiler register allocation.]
[This start kit is priced at] $6800.
In addition to the development tools provided by Intel, a broad range
of products supporting the 80960 architecture are being offered by
independent software and hardware vendors [including] Bauer Electronics
[Postscript clone], GenRad, Advanced Computer Techniques [compilers],
JMI, Logic Automation, Mentor Graphics [CAD design support], Ready Systems
[Real-time kernel], and Tartan Labs [Ada compiler].
--
The 80960KA and the 80960KB are both available in 20MHz CHMOS* III
configurations. Both embedded processors operate at a sustained 7.5 MIPS
and 15K Dhrystones rates. The 80960KB is priced at $390 in 100-piece
quantities, and is packaged in a 132-lead pin grid array. The 80960KA,
available in the fourth quarter of 1988, will be $174 in 100-piece quantities.
[The KB is available in quantity now.] Intel plans to offer 25MHz versions
of the two embedded processors in early 1989.
For more information, call a local Intel sales office or 1-800-548-4725,
or write Intel Corp., Literature Dept. #W427, 3065 Bowers Ave, Santa Clara,
CA 95051.
[Other interesting information: the 80960 silicon has been used extensively
inside Intel since early 1986, and has run (literally) millions of lines of
code in a variety of applications. The chip is *very* well debugged.
The reference to "parallelism and modualr features" in the first paragraph
is a reference to other materials which allude to (near) future
implementations which will be able to execute three instructions in the
same clock cycle. The 80960KA and KB currently can overlap two instructions
in certain cases. The KA and KB implement "scoreboarding" of registers and
condition codes to allow multiple instruction execution.
This scoreboarding allows the 80960 architecture to hide the details of its
instruction pipeline, allowing complete binary software compatibility with
future implementations with different pipeline restrictions.
The 80960 is a three-address load/store architecture with 32 general
registers, 16 standard ("global") registers, and 16 ("local") registers
that are provided fresh for a routine invoked by the "call" instruction.
Implementations cache multiple sets of these local registers on chip, flushing
previous sets to memory. The KA and KB store four sets on chip, for a total
of 80 on-chip general registers.
More Later....]
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