is813cs@pyr.gatech.EDU (Cris Simpson) (01/30/89)
I am having trouble figuring out the INTR abilities of the 8255A. I understand that the 8255A signals the x86 on the INTR line, then the x86 asserts INTA, and then reads the 'vector type' from the data bus. The question: How does the 8255A set up the byte representing this 'vector type'? Yes, I have RTFDataSheet. No, please don't post responses, I'll summarize if anyone cares. Thanks, cris
smith@iwblsys.UUCP (Mickey Smith) (01/31/89)
From article <7184@pyr.gatech.EDU>, by is813cs@pyr.gatech.EDU (Cris Simpson): > > I am having trouble figuring out the INTR abilities of the 8255A. > I understand that the 8255A signals the x86 on the INTR line, then > the x86 asserts INTA, and then reads the 'vector type' from > the data bus. The question: How does the 8255A set up the byte > representing this 'vector type'? > > Yes, I have RTFDataSheet. No, please don't post responses, I'll > summarize if anyone cares. > > Thanks, > cris At last look the 8255A was and still is and Peripheral Interface component (i.e. parrallel port chip) and not an interrupt controller. If you are speaking of the 8259A interrupt controller that's different, and the answer goes something like this. The vector on the bus at INTA time is taken from the interrupt input pin number the signal was generated from. Ofcourse the format of this depends upon the system mode of the 8259A(an 8080/8085 or 8086 system). Assume 8086 mode, 1. One or more of the external interrupt lines goes active. 2. The 8259A sends the CPU an INT. 3. The CPU acknowledges and responds with an INTA. 4. The 8259A sets the highest in_service_register interrupt bit and resets the interrupt_request_register bit. 5. The 8259A sends the highest priority interrupt during the second INTA cycle initate by the CPU. 6. And this completes the interrupt cycle, the in_service_register will remain set until an end_of_interrupt command. -- Mickey Smith, Regional Software Specialist | Opinions are my own and not Intel Corporation | that of my employer. 7071 Orchard Lake Road | W. Bloomfield, MI 48332 (313) 851-8096 | So there!!
cww@ndmath.UUCP (Clarence W. Wilkerson) (01/31/89)
In article <7184@pyr.gatech.EDU>, is813cs@pyr.gatech.EDU (Cris Simpson) writes: > > I am having trouble figuring out the INTR abilities of the 8255A. > I understand that the 8255A signals the x86 on the INTR line, then I believe that the interrupt is handled by the 8259. On an 8085 system, the processor sends the 8259 3 INTA- signals. After the first, the 8259 emits a CALL opcode, then two more bytes of prprogrammed interrupt vector. On an 8088, the CALL is not emitted. I don't think the 8255 has any interrupt capabilities. The Zilog 8 bit PIO probably has something like you describe.