vishin@helios.cs.duke.edu (Sanjay Vishin) (02/08/89)
Can somebody tell me what exactly a "Flyback Cycle" is ? All I know is that it has to do with an I/O device (controller) doing a DMA on its own rather than going though a DMA controller or am I wrong !?? Thanks vishin@simon.mcnc.org vishin@cs.duke.edu
mlawless@ncrwic.Wichita.NCR.COM (Mike Lawless) (02/09/89)
In article <13433@duke.cs.duke.edu> vishin@helios.cs.duke.edu (Sanjay Vishin) > > Can somebody tell me what exactly a "Flyback Cycle" is ? > > All I know is that it has to do with an I/O device (controller) doing a > DMA on its own rather than going though a DMA controller or am I wrong !?? Perhaps you mean "Fly-by". This refers to a DMA cycle in which a Memory Read and an I/O write (or vice versa) occur on the same bus cycle. Some DMA controllers (the built-in DMA in the 80186/8 processor is a notorious example) require two bus cycle to accomplish one transfer; the first fetches the data and places it in a holding register, and the second writes it to the destination. Fly-by DMA takes advantage of the fact that many I/O devices do not depend on the address bus for DMA; the DMA Acknowledge signal combined with the I/O read or write strobe is sufficient to complete the transfer on the I/O side. Therefore, the address bus can be dedicated to accessing memory during DMA. Obviously, then, fly-by DMA is preferable in high-performance designs, because the bus bandwidth is doubled for DMA transfers. -- Mike Lawless, NCR E&M Wichita, Box 20 (316) 636-8666 (NCR: 654-8666) 3718 N. Rock Road, Wichita, KS 67226 Mike.Lawless@Wichita.NCR.COM {ece-csc,hubcap,gould,rtech}!ncrcae!ncrwic!Mike.Lawless {sdcsvax,cbatt,dcdwest,nosc.ARPA}!ncr-sd!ncrwic!Mike.Lawless