cgs@umd5.umd.edu (Chris G. Sylvain) (03/04/89)
In article <169.24081110@muadib.FIDONET.ORG> Sean.Conner@f7.n369.z1.FIDONET.ORG (Sean Conner) writes: >>Chris Sylvain writes: >>[1 msec with interrupts disabled when using BIOS Int 15h extd. mem. service] >> To further examine the problem, I would like to know what the expected >> frequency of interrupts is for the AT I/O chip (the 16450?) and the >> XT I/O chip (8540?) when operated at 9600 baud. > > Well, at 9600 [...] a Received-Data interrupt every 1.04 milliseconds. > [...] Hope that helps somewhat. > -Sean Thanks for responding to the item I posted. Yours was the only response I received from the comp.sys.ibm.pc folks. I did receive a few responses from the comp.sys.intel folks, and the best one follows (thanks to all who did respond! please don't think it wasn't appreciated because this ain't yours): ---------- cut here ---------- From watmath!softart!riml@uunet.UU.NET Wed Feb 22 06:30:03 1989 Subject: Re: Async interrupt frequency The 16450 and 8250B are functionally identical when dealing strictly with serial I/O. There are electrical differences, and the 16450 has a couple of scratchpad RAM bytes that the 8250 lacks. This is from a great deal of programming and hardware experience, and data sheets on all the 8250 chips, from the first (8250) through to the 8250A, 8250B, and the 16450. None of these chips have a FIFO on input or output so you must read them quickly to avoid losing data! (Naturally, the shift register can fill up with the next character while the previously received character is waiting to be read. But you can't send another character to the transmit buffer until the currently transmitting character has emptied out of the buffer.) To answer your question: at 9600 baud, assuming 8 bits, no parity, and one stop bit, you are sending and receiving 960 characters per second worst case. This assumes no delay between characters. If we also assume that the transmitter interrupts fall EXACTLY between the receiver interrupts, this gives you an absolute worst case interrupt frequency of 1920 per second. The time between interrupts is very easy to determine. :-) BEWARE: if you wish to make your interrupt handler portable and usable with both the 16450 and 8250B chips, you MUST check for other serial interrupt conditions in your interrupt handler. To be clearer: Read the IIR register, #2, to determine the interrupt condition. These are prioritized. Service the interrupt condition. (Receive interrupts MUST read the input byte or you will get continuous interrupts because the condition will not go away.) After you're done servicing the interrupt condition, loop back and read the IIR register -- do it all over again until there is a NO INTERRUPT condition (bit 0 is a 1). Don't forget to send a SPECIFIC END OF INTERRUPT command to the 8259 PIC when you're done handling all the serial conditions, and you are exiting the interrupt handler. This lets the PIC chip know that the interrupt condition is over, and it can continue with any other equal or lower priority interrupts that may be pending. Michael A. Barnstijn V.P. Software Systems USENET: ...!uunet!watmath!softart!riml Research In Motion Limited PHONE: (519) 888-7465 Suite 6, 465 Phillip Street, Waterloo, Ontario, Canada N2L 6C7 My opinions sometimes reflect my company's opinions, and sometimes not. It depends on how many shares I have at the time :-) ---------- end info ---------- -- --==---==---==-- .. So rested he by the Tumtum tree, .. ARPA: cgs@umd5.UMD.EDU BITNET: cgs%umd5@umd2 UUCP: ..!uunet!umd5.umd.edu!cgs