holder@druhi.ATT.COM (Mike Holder) (04/20/89)
Apologies if you've seen this before, but I think my news posting program trashed my last attempt. I'm developing an Operating System on an 80286, and I'm having some problems handling interrupts. Here's the setup: Processor runs in Protected Mode with processes running with privilege level 3 using the large memory model and the kernel running with privilege level 0 in the small memory model. We handle device interrupts through a Programmable Interrupt Controller, and these device interrupts are handled via Interrupt Gates in the Interrupt Descriptor Table. Interrupt Gates are supposed to disable interrupts (zero the Interrupt Flag) when an interrupt is handled. However, I have a logic analyzer trace that shows a clock interrupt being handled by the kernel, and another (tty character) interrupt comes in just as the clock interrupt handling routine gets started. Since the kernel was architected assuming interrupts were locked out once the kernel was reached, the kernel ends up crashing later on when it attempts to return to the interrupted process. So, how can the processor get a second interrupt in once the first interrupt vectors through an Interrupt Gate? Is there some window of time between the hardware reading the Interrupt Gate and the time interrupts actually get disabled? Any help would be appreciated. Mike Holder holder@druhi.att.com AT&T Bell Laboratories ..!att!druhi!holder 12110 N. Pecos Street Denver, CO 80234 (303) 538-3929