[comp.sys.intel] High Level CPU Architectures

mch@ukc.ac.uk (Martin Howe) (05/17/89)

Hi there. Some time ago I read in Electronics & Power (an IEE journal) and
later in BYTE about a Scottish hi-fi manufacturer called Linn who have deigned
a very high level CPU for their in-house computing work. This CPU, much in
the spirit of the Intel 80432, is a recursively microcoded object-orientated
machine, currently implemented as the "Hades" a triple width VME Eurocard
stuffed with WIETEK chips (I think) plus some associative memory devices.

I have for some time been interested in the RISC vs CISC debate and have often
wondered why no one has tried this approach before (apart from Intel's 432, and
I don't know HOW similar that was to the Rekursiv architecture). I was quite
amused at a quote made by a Linn employee in the E & P article to the effect
that current CISCs are the worst of both worlds -- too high level for fast
execution of INDIVIDUAL instructions, while these instructions are not powerful
enough to justify their (relatively) slow execution time. The Intel 80486 will
have made *some* nonsense of this with the [expected] very wide prefetch bus
(at least from the cache) and RISC core etc, but overall that statement summed
up feelings that I have had for some time.

Does anyone care to comment on the current state of the art in High Level CPU's
(object orientated or not) or even better, suggest a few reasons why this sort
of thing isn't more common (without starting another flame war of course :-) ?

For my money, I'd be interested to see what happened if Intel had a go. "One
segment per object" has been debated recently and if Intel have any sense,
32-bit segment values for the 86 series can't be far off, [unless Intel wants
to let it die a natural death after the 80<whatever>86 so to let the i860
take over]. This would make it interesting to try piggybacking a Linn style
object descriptor system onto the (32 bit) segmentation mechanism of the 80?86.

With the technology available for 1MTr (MTr = Mega Transistor :-) chips, RISC
cores and the like, who knows, the 80432 might even have been a viable
proposition had it been designed this year or last.

Please note, that I'm predominantly interested in the technical aspects
of all this, rather than commercial ones, so if anyone has any LONG commercial
discussion to add to this, I'd be grateful if they could use a (slightly)
different follow-up heading.

Anyone ?
-- 
Martin Howe                  (This posting is private, and NOT on behalf of UKC)