ccplumb@lion.waterloo.edu (Colin Plumb) (03/21/90)
The Intel 80186 data sheets I've looked through claim to have reduced cycle counts for some instructions over the 8086. But some of the numbers look rather suspect. Acording to the data sheet (I'm quoting the 1986 Microsystem Components Handbook, but other books from 1983 to 1988 and by AMD as well give the same numbers): move memory to register is 9 cycles move register to memory is 12 cycles move memory to segreg is 9 cycles (okay, the same) move segreg to memory is 11 cycles (1 cycle *less*???) move memory to accumulator is 9 cycles (same as mem->reg) move accumulator to memory is 8 cycles (lots less than reg->mem) push register is 10 cycles push memory is 16 cycles pop register is 10 cycles pop memory is 20 cycles add, sub, or, and, etc. memory with register to either is 10 cycles pusha is 36 cycles popa is 51 cycles Is it true that moving a register to the accumulator and storing it is faster than storing it directly? Is it true that mem = mem op reg takes the same time as reg = mem op reg? Is it true that mem = mem op reg takes less time than mem = reg? Is it true that push reg is faster than mem = reg? Is it true that pop memory is slower than push memory? Is it true that pusha is 15 cycles faster than popa? And does anyone know the cycle count for an INTR (external interrupt) sequence? Presumably it's in the same range as the 45 or 47 for an INT instruction, but I'd be curious if anyone knew. Thanks if you know the gory details. -- -Colin