art@pilikia.pegasus.com (Art Neilson) (07/04/90)
I recently learned of a bug in the 80386DX processor version SX211.
The latest release of ISC UNIX 2.2 enables instruction pipelining,
causing my system to hang during installation of this new release.
I tried putting my drive and controller in another 386 box with a
different CPU, the OS installed fine. I put the drive and controller
back in my system and tried booting the system. The kernel panics
and dumps everytime it loads. Can anyone confirm the pipeline bug
in the 80386DX processor version SX211 and explain just what instruction
pipelining is ? I was told the SX219 version doesn't have this problem.
Is this the most current incarnation or the 80386DX ? BTW, my processor
reads as follows:
Intel
80386DX-33 IV
SX211
--
Arthur W. Neilson III | ARPA: art@pilikia.pegasus.com
Bank of Hawaii Tech Support | UUCP: uunet!ucsd!nosc!pegasus!pilikia!artdhinds@portia.Stanford.EDU (David Hinds) (07/05/90)
In article <1990Jul4.084846.7262@pilikia.pegasus.com> art@pilikia.pegasus.com (Art Neilson) writes: > >I recently learned of a bug in the 80386DX processor version SX211. >The latest release of ISC UNIX 2.2 enables instruction pipelining, >causing my system to hang during installation of this new release. >I tried putting my drive and controller in another 386 box with a >different CPU, the OS installed fine. I put the drive and controller >back in my system and tried booting the system. The kernel panics >and dumps everytime it loads. Can anyone confirm the pipeline bug >in the 80386DX processor version SX211 and explain just what instruction >pipelining is ? ... This sounds very unreasonable to me. Instruction pipelining refers to overlapping the execution of several instructions as they pass through different functional units of the chip. So, for example, while one instruction is being fetched, another is being decoded, and another is being executed. This is an intrinsic feature of the 80386 - it is not something that can be switched on and off by an operating system. The 80386 also has an "address pipelining" mode which allows some overlap of memory accesses. This mode is affected by the sort of memory system attached to the CPU, but is also not subject to software control. It seems much more likely that there is some other incompatibility responsible for the failure of your Unix to load. It isn't inconceivable that there is a bug in the 386DX, but I haven't heard of any, and it could not be as you describe. -David Hinds dhinds@popserver.stanford.edu
mslater@cup.portal.com (Michael Z Slater) (07/06/90)
>>...and dumps everytime it loads. Can anyone confirm the pipeline bug >>in the 80386DX processor version SX211 and explain just what instruction >>pipelining is ? ... > >This sounds very unreasonable to me. Instruction pipelining refers >to overlapping the execution of several instructions as they pass through >different functional units of the chip. So, for example, while one Various versions of the 386 have different assortments of bugs; at least one version had a problem with _bus_ pipelining, which is entirely separate from instruction pipelining. There may well be other bugs that are associated with the instruction pipeline. The first chips marked DX were (by coincidence) the D-step revision of the masks. Starting in mid-89, Intel began shipping these parts; they were the first to use the 1-micron process, and the first to have good yield at 33 MHz. Unfortunately, they also had a new, serious bug. Under just the right conditions, including instruction decode queue full, paging enabled, instructions fetched using pipelined bus cycles, and then a TLB miss, the prefetch queue is corrupted. This is obviously catastrophic, should the proper set of conditions exist. The only condition that can be readily avoided is to not use pipelined bus mode. This bus mode is designed to allow more access time when using DRAM- only systems, but is not used in systems with caches. This makes the bug harmless for the majority of systems. So, this long-winded answer may or may not apply to the problem that began this thread. I don't know when Intel fixed the problem, or even if they fixed it. In 1989, they continued to ship older 1.5-micron process parts to 20- and 25-MHz customers that used pipelined bus mode. Can anyone at Intel fill us in on the 386 revision history and markings? Michael Slater, Microprocessor Report mslater@cup.portal.com 874 Gravenstein Hwy. So., Suite 14, Sebastopol, CA 95472 707/823-4004 fax: 707/823-0504