[comp.sys.intel] i82596 EtherChip Book Question

mat@phx.mcd.mot.com (12/05/90)

I'm looking for a clarification from the "82596 User's Manual"
(ethernet chip).  I'm using the chip in Big Endian mode and was
confused about some of the text and figures in chapter 5, "Big Endian
Software Interface". The following figure and text are from that
chapter, page 5-33.


                      Linear Mode (Big Endian)
   31                             16 15                             0
   |                               | |                              |
   +-+-+--+-+-+-+-+-+-+-+-+-+-+-+-+-+--+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 0 |C|B|OK|0 0 0 0 0 0 0 0 0 0 0 0 0|EL|S|I|X X X X X X X X X X|0 0 0|
   +-+-+--+-+-+-+-+-+-+-+-+-+-+-+-+-+--+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+
 4 |    LINK ADDRESS LOW WORD       |      LINK ADDRESS HIGH WORD    |
   +-+-+--+-+-+-+-+-+-+-+-+-+-+-+-+-+--+-+-+-+-+-+-+-+-+-+-+-+-+-+-+-+

[ some text from page removed ]

CMD(Bits 16-18)     - The NOP command. Value: 0h

[ some more text from page removed ]


It appears to me that the mistake is in the text that defines the CMD,
where it refers to "Bits 16-18". The command is actually in bits 0-2.
If my assumption is not correct, possibly the figure is labeled
incorrectly and the bit labeling should be 15-0,31-16. The real heart
of my confusion is in the LINK ADDRESS, which is a 32bit pointer to
another structure. If the picture is correct it is stored LOW WORD -
HIGH WORD which means pointers will have to be manipulated before
being used on a Big Endian machine. If the figure is wrong and the
text is correct, the pointers will work fine but all of my structures
definitions will be wrong.

Does anyone have experience with the 82596 in Big Endian mode, or
possibly just the definitive truth on this matter :-).

Book info:
	82596 USER'S MANUAL
	Copyright Intel Corporation 1989
	Chapter: 5 - Big Endian Software Interface
	Page: 5-33

Thanks

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