sam2y@batik.cs.Virginia.EDU (Steven A. Moyer) (01/06/91)
-- I'm looking for information concerning how cache lines are filled on the i860 processor. In particular, does the i860 make use of the NA# signal (assuming it is support by the memory subsystem) in order to pipeline cache line reads? In measuring load rates on an RX node, I can obtain a rate of 20M/sec using the pfld instruction. With the cache flushed so that there is no write-back, I can only obtain a rate of 10M/sec using the fld instruction. Yet, the hardware reference manual seems to imply that the cache controler does indeed take advantage of memory pipelining when available. Any ideas? +--------------------------------------------------------------------+ | Steven Moyer | THIS SPACE FOR RENT | | University of Virginia | | | | "Just a rebel without a clue..." | | E-mail: sam2y@virginia.edu | - The Replacements | +--------------------------------------------------------------------+