sam2y@batik.cs.Virginia.EDU (Steven A. Moyer) (12/20/90)
I'm looking for information concerning how cache lines are filled on the i860 processor. In particular, does the i860 make use of the NA# signal (assuming it is support by the memory subsystem) in order to pipeline cache line reads? In measuring load rates on an RX node, I can obtain a rate of 20M/sec using the pfld instruction. With the cache flushed so that there is no write-back, I can only obtain a rate of 10M/sec using the fld instruction. Yet, the hardware reference manual seems to imply that the cache controler does indeed take advantage of memory pipelining when available. Any ideas? +--------------------------------------------------------------------+ | Steven Moyer | THIS SPACE FOR RENT | | University of Virginia | | | | "Just a rebel without a clue..." | | E-mail: sam2y@virginia.edu | - The Replacements | +--------------------------------------------------------------------+
wpd@ece.arizona.edu (William P. Delaney) (06/29/91)
I seem to recall hearing about an undocumented instruction in protected mode x86 processors called LOADALL, or something like that. Does anyone have any technical information on this? I would be interested in the following details in particular: * opcode value(s) * precise effects * inverse operation (i.e. SAVEALL?) Thanks, Bill Delaney (wpd@ece.arizona.edu)