dyer@spdcc.COM (Steve Dyer) (05/31/87)
In article <90@spdcc.COM>, dyer@spdcc.COM (Steve Dyer) writes: >The Inboard can run at either 8 or 16mhz with its cache off or on. >At power-up or reboot, it resets to an intermediate speed; I believe >it's 8mhz, cache on. Intel provides a couple of DOS programs which >toggle the speed between the four different possibilities. Unfortunately, >if you're running XENIX, you're presently stuck with this default >speed, and can't easily take advantage of the 16mhz/cache combo. >I plan to write a kernel driver which can perform the necessary >OUT instructions to accomplish this. /* * Dumb device-driver interface to Intel Inboard/386 card * to switch the operating speed of the Inboard between * 8mhz and 16mhz and to turn the cache on or off, as in * the DOS program SPEED.COM provided by Intel. * Tested under SCO XENIX V version 2.1.3 * * Copyright 1987, Steve Dyer, S.P. Dyer Computer Consulting, Cambridge MA * You may use and distribute this code freely as long as this copyright * notice remains in the code. * * Add the following lines to cdevsw in c.c: extern inopen(); * For SCO XENIX 2.1.3: inopen , nulldev , nodev , nodev , nodev , 0, * For SCO XENIX 2.2 (note: untested) "in" , inopen , nulldev , nodev , nodev , nodev , 0, 0, * I used major device 31, as it's unused in both 2.1.3 and 2.2 * * Very simple to use -- minor device number of special file * contains bits for the 4 different states. Accomplished * by 'opening' the special file corresponding to the desired state: * * Bit 0: Cache (0 == off) * Bit 1: Speed (0 == 8mhz) * * Minor device no: 0 - 8mhz, no cache * 1 - 8mhz, cache on * 2 - 16mhz, no cache * 3 - 16mhz, cache on * This may or may not correspond to the Intel convention of SPEED.COM * (although its arguments range from 1-4, not 0-3. However, the * intermediate settings aren't documented regarding what is on or off. * * Usage: # /etc/mknod /dev/nocache8 c 31 0 # /etc/mknod /dev/cache8 c 31 1 # /etc/mknod /dev/nocache16 c 31 2 # /etc/mknod /dev/cache16 c 31 3 * Then, one of (given in approximate increasing order of speed): # echo < /dev/nocache8 # echo < /dev/nocache16 # echo < /dev/cache8 # echo < /dev/cache16 * * I didn't bother with placing super-user checking in the open code; * simple UNIX-style permissions on the special files should suffice. * In most cases, adding the following line to /etc/rc is all that is needed: echo < /dev/cache16 */ #include "../h/types.h" #include "../h/sysmacros.h" #define CACHE_ON 1 #define HIGH_SPEED 2 #define CACHEADDR 0x670 #define SPEEDADDR 0x674 #define DEBUG #ifdef DEBUG static char *inmsg[] = { "8mhz, cache off", "8mhz, cache on", "16mhz, cache off", "16mhz, cache on" }; #endif inopen(dev, flags) dev_t dev; int flags; { register unsigned char min = minor(dev); register int s; if (min > 3) return; /* don't bother with u.u_error */ s = spl7(); /* just to be sure */ /* The Intel support person on the phone said that */ /* 0x80 turned ON 16mhz mode. However, my benchmarks */ /* argue that she had her bits flipped */ outb(SPEEDADDR, (min & HIGH_SPEED) ? 0x0 : 0x80); outb(CACHEADDR, min & CACHE_ON); splx(s); #ifdef DEBUG printf("\nInboard: %s\n", inmsg[min]); #endif } -- Steve Dyer dyer@harvard.harvard.edu dyer@spdcc.COM aka {ihnp4,harvard,linus,ima,bbn,halleys}!spdcc!dyer