chuqui@nsc.UUCP (Chuq) (08/03/84)
I want to thank the people who took time to respond to my inquiry about instrumenting caches. As it turns out, there doesn't seem to be any way to directly monitor cache activity without using a number of logic analyzer tied directly to the bus. One way of indirectly monitoring it is to turn the cache on and off during timesharing, which can be done (on the vax, at least) in console mode by poking at appropriate places (see the hardware manual for the right places. Note-- if you can't figure it out from the hardware manual you probably don't want to try it). I've been delving into the innards of the kernel with vmstat and gprof/kgmon trying to track down where all of our CPU cycles have been going and have found something that looks interesting. Our 4.2 780 is still running DZ's using the dma simulation code. We are getting an enormous number of interrupts generated (with 8 DZ boards, who wouldn't???). Each interrupt seems to be dropping through the Swtch process scheduler routine, which sets up a new process for the CPU to play with. Needless to say, we are spending a LOT of time scheduling processes. I've timed some I/O intensive routines on our 780 and our 750 (which does have DH's) and found that the amount of time in Switch is about 30% for the 780 and about 2.5% for the 750. Non-trivial, to say the least. We were under the impression that the dma simulation code kept the system from dropping through the scheduler, but this doesn't seem to be the case. Has someone else found a way to keep this enormous DZ overhead from crippling the system? From all indications the best we can do is about a 765. I've got people looking into buying DH's (of course...) but I was wondering if someone had a software fix out there. Has anyone else out there looked into this? chuq s -- From the depths of the Crystal Cavern: Chuq Von Rospach {amd,decwrl,fortune,hplabs,ihnp4}!nsc!chuqui nsc!chuqui@decwrl.ARPA Dreams, dreams, enchanter! Gone with the harp's echo when the strings fall mute; with the flame's shadow when the fire dies. Be still, and listen.
thomson@uthub.UUCP (Brian Thomson) (08/07/84)
From nsc!chuqui ... > Our 4.2 780 is still > running DZ's using the dma simulation code. We are getting an enormous > number of interrupts generated (with 8 DZ boards, who wouldn't???). Each > interrupt seems to be dropping through the Swtch process scheduler routine, > which sets up a new process for the CPU to play with. Are you sure you're not mistaking idle time for "setting up a new process"? The idle loop is in the Swtch routine. On a 4.2 780 here, I once put 25000 chars/sec out through the DZ pseudo-DMA code and had cpu to spare. -- Brian Thomson, CSRI Univ. of Toronto {linus,ihnp4,uw-beaver,floyd,utzoo}!utcsrgv!uthub!thomson