wolf@cadeta.UUCP (Wolf Herda) (02/10/88)
Has anyone been able to successfully use make using the MAKEFLAGS macro? For example, consider the following makefile. | foo: foo.c | $(MAKE) $(MAKEFLAGS) foo When entering the make command, it gives the following error message. | make b foo | Make: Don't know how to make b. Stop. | *** Error code 1 | | Stop. It seems that the MAKEFLAGS macro is replaced with the 'b'. If the command is "make -n", then it tries to "make bn foo". I think the SCO make has a bug, but before I call them, I thought I'd see if anyone else is familar with this. Comments, suggestions, ??? For what it is worth, I'm running Xenix-286 SysV release 2.2.1, using the 2.2 development system. -- Wolf Herda Autodesk, Atlanta (404) 998-8095 gatech!cadeta!wolf