friedl@vsi.UUCP (Stephen J. Friedl) (02/21/88)
Netpeople,
I haven't seen this mentioned anywhere so I thought I would
post this information from _Electronics_ magazine dated February
18, 1988. The International Solid State Ciruits Conference held
in San Francisco had some pretty neat technology announcements.
If this is not the best place to post this somebody please E-mail
me a note.
************* The Next Wave: 16-Mbit DRAMs from Japan (pg 68)
"An announcement concerning dynamic random-access memories
at the ISSCC in recent years has almost always had the ability to
astound, often leaving attendees shaking their heads in amaze-
ment, and in the case of U.S. engineers, not a little regret and
perplexity. This year's meeting in San Francisco is no excep-
tion.
"Scarcely has production begun on 1-MBit DRAMs and ap-
proached the sampling stage on a few 4-Mbit circuits than the
16-Mbit DRAM is on the scene -- not from one source but from
three. And all of them are Japanese. Hitachi Ltd. is showing a
16-Mbit design employing a transposed data-line structure;
Matsushita Electric Industrial Co.'s device has an open-bit-line
architecture; and Toshiba Corp. is demonstrating a unique design
that incorporates a serial 1-Mbit high-speed read/write mode.
"But if the efforts described so far by these three com-
panies are any indication, there are considerable technical hur-
dles left to overcome. It will be at least 1990 before such dev-
ices begin appearing in sample quantities.
[general comments on how nice it will be to have more mega-
bytes, plus notes on fabrication technology. These devices are
likely to run in the 60-ns access time range.]
************* Five Blazing Fast CMOS SRAMs are Coming (pg 69)
"As eye-catching as the 16-Mbit dynamic random-access
memories may be, the development that will have a more immediate
effect on the way memory is implemented is the new breed of stat-
ic RAMs combining 1-Mbit density with blazing speed. Five such
CMOS devices -- three from Japan and one each from the U.S. and
the Netherlands -- emerged at this year's ISSCC boasting access
times ranging from 14 to 30 ns. The entries come from Japan's
Fujitsu Ltd., Hitachi Ltd., and Mitsubishi Electric Corp, as well
as from IBM Corp.'s General Technology Division in Esssex Junc-
tion, Vt., and Philip's Research Laboratories in Eindhoven, the
Netherlands.
"Other than using CMOS as the base process, the five SRAMs
have little in common. Four designs -- from IBM, Hitachi, Mitsu-
bishi, and Philips -- are built around a six-transistor cell for
high-speed. Fujitsu Ltd. has instead opted for a four- transis-
tor design with polysilicon resistor loads to achieve high densi-
ty. The Philips chip is organized as 128 K by 8 bits, while
those from Fujitsu and Hitachi feature a 256-K-by-4-bit architec-
ture. The IBM SRAM can be configured by laser personalization
into 128 K by 8 bit, 256 K by 4 bit, or 1 M by 1 bit. The
Mitsubish chip boasts a 1-M-by-1-bit organization, dynamically
reconfigurable for testing to 256 K by 4 bits.
[a bland paragraph on impact of more megabytes]
"The most flexible 1-Mbit SRAM design is IBM's. In addition
to the three organizations, it can also be configured to run
asynchronously, with static-column and chip-enable speed-up
modes; or synchronously, with a fast-page or static-column mode.
As an asynchronous device, access time is 34 ns. In static
column mode, access time is 33 ns, and in the chip-select speed-
up mode, 29 ns. As a synchronous SRAM, access time is 29 ns,
with a fast-page-mode speed of 24 ns.
"To achieve a size of about 58 um^2 for the six-transistor
cell, the IBM device uses a 0.9-um retrograde n-well polysilicon
CMOS process with two metal layers, one of tungsten and one of
aluminum. Active power dissipation is 225 mW in the synchronous
mode and 230 mW in the asynchronous. Consisting of four qua-
drants of 256 Kbits partitioned into eight blocks of 32 Kbits
each, the device has a chip area of 10.8 by 8.5 mm^2. It can
operate off either 3.3- or 5-V supplies.
"Departing from the six-transistor approach is the 256-K-
by-4-bit SRAM from Fujitsu. Despite its use of the traditionally
slower four-transistor SRAM cell, it achieves an access time of
18 ns, albeit at some cost in power dissipation -- 350 mW active
and 10 mW standby. This performance was achieved by using a
sense amplifier with four stages, an aluminum word line, and a
0.7 um-gate transistor, and constructed using p-type substrate
with an n-well CMOS process.
"Sacrificing flexibility for a better speed/power trade-off
is the 128-K-by-8-bit Philips offering. This 5-V-only design
sports a 25-ns access time with an active power dissipation of
only 75 mW. Fabricated in 0.7-um twin-tub, single polysilicon,
double-metal CMOS process, the chip features a six-transister
cell measuring 60 um^2 -- only slightly larger than that of the
IBM design.
"At Hitachi, meanwhile, designers opted to go all out for
speed: the company's six-transistor offering is capable of 15-ns
access time but with power dissipation of 250 mW active and 10
microamperes standby. Remarkably, this power is achieved with a
cell size of 44 um^2 and a chip size of about 90 mm^2 -- only
about 10% larger than the four-transistor Fujitsu entry. What
makes small size possible, the designers say, is a unique word-
decoder design in which the number of p-channel and n-channel
transistors used in constructing the NAND gates can be greatly
reduced. Hitachi uses a relatively conservative 0.8-um double-
polysilicon, double-metal CMOS process.
"Mitsubishi's entry, also with six transistors, employs a
0.7-um double-metal, twin-well CMOS process process and fast
word-line selection coupled with highly sensitve sense amplifiers
to achieve its [are you sitting down?] 14-ns access time. Trench
isolation yields a small cell size: 41.6 um^2. The memory also
offers an unusual variable bit organization feature controlled
from one of its 28 pins. With this, the usual 1-M-by-1 organiza-
tion can be changed to 256 K by 4 bits to reduce testing time." -
Bernard C. Cole
************* From "Electronics Newsletter", page 21
"AT&T will start briefing customers on Version 4.0 of Unix V
this summer. A new version of AT&T Co.'s Unix System V is in the
offing for late 1989 and yet another version is taking shape. At
last week's Uniforum show in Dallas, AT&T announced it would
start briefing computer companies and software developers about
Unix System V Version 4.0 this summer. The company also used the
show to give licensees a peek at what's in store: Sun Microsys-
tems Inc.'s Remote Procedure Call and Network File System
software will be added, along with come features of Microsoft
Corp.'s Xenix System V and others that are derived from Berkeley
Unix. Meanwhile, Bill Joy, Sun's vice president of research and
development, is setting up a group to rewrite the Unix kernel in
C++ [!], an object-oriented extension to the C programming
language. This kernel will be used in Version 5 of Unix System
V, and Joy says it should make the operating system easier for
licenses to enhance."
------------
Other articles in this issue talk about Intel's 4-Mbit EPROM
(pg 72), Rockewell's 8-bit, 150-MIPS GaAs processor (pg 74),
Motorola's 17-MIPS RISC chip due out this spring (pg 83), and a
fascinating piece on ferroelectric effect non-volatile SRAMs
(note: ferroelectric is *not* core memory) on pg 91.
This is one of most exciting technology issues I've seen in
_Electronics_ -- find a copy if you can.
--
Life : Stephen J. Friedl @ V-Systems Inc/Santa Ana, CA *Hi Mom*
CSNet: friedl%vsi.uucp@kent.edu
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