mark@mips.COM (Mark G. Johnson) (11/05/88)
In article <3717@peora.ccur.com>, joel@peora.UUCP (Joel Upchurch) writes >Speaking of error checking. I wonder how many of the manufacturers of >computers using memory caching use parity checking on the cache memory >as well as the main memory? A lot of 386 machines have larger cache >memories than the original PC had as main memory. Not only the data in >the cache, but the translation addresses. And if the processor has >loadable microcode how about on the microcode control store? Many manufacturers go even further. Our M/2000 machine, for example, uses parity checking in the caches (which are built of 16Kx4 SRAMs) and _also_ ECC in the main memory (which is a pile of 1Mx1 DRAMs). Since the caches are write-through, a parity error in the cache is completely recoverable: simply go get a clean copy from main memory. This decision was based in large part upon the bitter experience we (and others!) had with a very popular machine which shall go unnamed here. Said machine had a (non-ECC, non-parity protected) cache built out of a particular SRAM vendor's fastest chips. These cache chips were particularly susceptible to power-supply-noise, so the cache data got corrupted rather too frequently. And, as cache errors were unrecoverable, the application program (& sometimes the OS) would crash. We (and others!) decided that customers didn't really like this sort of behavior, so we & they concluded that caches ought to be error-checked. { Yes, another "solution" might have been to reduce power-supply-noise and/or choose another SRAM vendor. But we and others didn't. } -- -- Mark Johnson MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086 ...!decwrl!mips!mark (408) 991-0208