jdm@a.cs.wvu.wvnet.edu (James D Mooney) (06/17/89)
AN OVERVIEW OF TRON Jim Mooney June 16, 1989 The following is some general information on the TRON project. I believe this information is current and correct as of June 1989, though it certainly is not complete. I apologize for any errors or omissions. A short annotated bibliography of English language publications is also included. The TRON project was begun in 1984 by Dr. Ken Sakamura at the University of Tokyo. Its ultimate objective is to support what is envisioned as "Highly Functionally Distributed Systems" or HFDS, that is, networks that span the globe, connecting large computers, personal workstations, and a multitude of "intelligent objects" such as appliances, environmental control systems, cameras, automobiles, etc., etc., in which computers are embedded. TRON stands for The Realtime Operating system Nucleus. The total project includes a specification for a TRON CPU chip, several types of operating system interfaces, and a number of auxiliary subprojects. Each project is defined by a set of specifications which focus on the interface and functionality and deliberate leave room for design variations. It is intended that the specifications be publicly available and it is hoped that many developers will produce implementations which meet the specifications. The OS subprojects include: ITRON (Industrial TRON), specialized for control of intelligent objects; BTRON (Business TRON), specialized for control of workstations; CTRON (Communication, Central and Common-Use TRON), specialized for managing processing on larger computers and communication between computers; MTRON (Macro TRON), intended to provide overall intelligent control to the HFDS. Other related projects that have been initiated under the TRON umbrella include TULS (TRON Universal Language System), a specification language for describing system interfaces; TAD (TRON Application Databus), a data format specification for information exchange; TACL (TRON Application Control-Flow Language), an interactive user-interface language for BTRON systems. Tobus, a system bus architecture. My own detailed knowledge is limited to CTRON. I will give what information I have on the other projects. The TRON CPU is a powerful (CISC style) 32-bit microprocessor extensible to 64-bit data paths and addresses. It is especially designed for ITRON and BTRON systems, but can run other types of systems as well. Versions of this chip have now been implemented independently by at least half a dozen Japanese manufacturers. ITRON is an OS interface specification for small realtime executives used in embedded applications such as robotics or factory automation. BTRON is a design for an OS program interface and human interface for high-performance, multilingual workstations. Each of these projects are designed to execute effectively using the TRON CPU, but initial implementations have used several other processors. Several companies have prototype implementations of each of these systems. CTRON is a very large specification for system interfaces appropriate on larger systems acting as network servers. The full specifications are now being published in 9 volumes expected to total over 3000 pages. These are still draft versions. Implementation work is in an early stage. MTRON and the newer subprojects are still in relatively early stages of development. The initial TRON papers and documents were all in Japanese. However, IEEE MICRO in 1987 devoted an entire issue to TRON (Vol. 7, No. 2, April 1987). This issue is still the best widely-available detailed introduction to the TRON project. Other occasional articles have appeared in English publications and conference proceedings. Most of these are cited in the attached bibliography. Dr. Sakamura remains the "guiding spirit" of most TRON projects. However, work continues today under the direction of a large industrial consortium called the TRON Association. This association was formed in Japan in 1986 and officially incorporated in 1988. Membership as of March 1989 included about 125 companies. Although all activities to date have taken place in Japan, participation in the TRON association has never been restricted by nationality. Membership is open to "corporate bodies and organizations that share the goals of the association." Annual dues range from 500,000 yen (about $4000 U.S.) to 3,000,000 yen (about $24,000 U.S.) depending on the degree of participation. The current membership list includes such familiar non-Japanese names as ASCII Corp., IBM, Intel, Motorola, Northern Telecom, Olivetti, Siemens, Texas Instruments, and Victor (some of these are represented by their Japanese divisions). The TRON Association conducts a variety of meetings and conferences. So far there have been two international conferences (in Tokyo) with English proceedings and translations. The proceedings have been published by Springer-Verlag's Tokyo division (see the bibliography). The TRON association also publishes the TRON Project Quarterly Report, in English and Japanese versions. Further information can be obtained from the TRON association: TRON Association 5th floor, Tomoecho Annex-II 3-8-27, Toranomon, Minato-ku Tokyo 105 JAPAN Tel: 81-3-433-6741 FAX: 81-3-433-5003 Dr. Sakamura himself can be contacted at the University of Tokyo: Dr. Ken Sakamura Dept. of Information Science Faculty of Science, University of Tokyo 3-1, Hongo 7-chome, Bunkyo-ku Tokyo 113 JAPAN Detailed specifications for at least some of the TRON projects are available for purchase. TRON Association membership is not required. I am acquainted only with the CTRON specifications. These have been published in preliminary versions in both Japanese and English. The "version 2" series is now appearing; version 3 is scheduled by the end of 1991. Because of their bulk they have been fairly expensive. A new publishing arrangement is planned to make these volumes available more economically by the end of 1989. for details, contact IOS Van Diemenstraat 94 1013 CN Amsterdam Netherlands or IOS PO Box 2848 Springfield, VA 22152-2848 USA The next international TRON Symposium is tentatively scheduled for December 5-6, 1989, in Tokyo. ANNOTATED ENGLISH LANGUAGE BIBLIOGRAPHY Datamation. Japan's TRON tactics. Datamation, Vol. 33, No. 19, Oct. 1, 1987, pp. 76/21 ff. (International edition). An early overview of the TRON project. Electronic Design. Instruction Set Architecture Prepares Systems for the 1990s. Electronic Design, Vol. 36, No. 3, Feb. 4, 1988, pp. 33 ff. A description and review of the TRON CPU architecture and its potential impact on the industry. Imai, Y., et al. An implementation based on the BTRON specification. in IEEE COMPCON Spring 1988 Digest of Papers, pp. 22-24. Kobayashi, M., et al. The software structure of extended nucleus based on the BTRON specification. Proc. 1987 Fall Joint Computer Conf., pp. 153-158. Sakamura, Ken (ed). IEEE MICRO Special issue on TRON. Vol 7, No. 2, April 1987. Articles include: The TRON Project; Architecture of the TRON VLSI CPU; Configuration of the CTRON Kernel; Introduction to ITRON; BTRON: the Business-oriented Operating System. Sakamura, Ken (ed.) TRON Project 1987: Open-Architecture Computer Systems (Proceedings of the Third TRON Project Symposium) Springer-Verlag, Tokyo, 1987 Proceedings of the first *international* (English language) TRON symposium, Tokyo, November 1987. Includes a TRON overview; overviews of ITRON and BTRON plus implementation papers; overview of CTRON plus several design papers; overview of TRON CPU plus design and implementation papers. Sakamura, Ken (ed.) IEEE MICRO special issue on the 32-Bit Microprocessor in Japan. Vol. 8, No. 2, April 1988. Description of three new microprocessor implementations, two of which are TRON CPUs, and related projects. Sakamura, Ken (ed.) TRON Project 1988: Open-Architecture Computer Systems (Proceedings of the Fifth TRON Project Symposium) Springer-Verlag, Tokyo, 1988 Proceedings of the second international TRON symposium, Tokyo, December 1988. Includes design concepts for TULS and MTRON; ITRON implementation papers; BTRON concepts and implementations; TACL language; CTRON design, implementation, and commentary; lots of TRON CPU implementations. Sakamura, Ken, and Sprague, Richard. The TRON Project. BYTE, Vol 14, No. 4, April 1989, pp. 292-301. An up-to-date overview of the status of TRON, with emphasis on BTRON and the TRON CPU. A sidebar by editor Janet Barron discusses TRON's prospects for acceptance in the U.S. Sakamura, Ken (ed.). Special Issue of Microprocessors and Microsystems on the TRON Project. To appear, Sept. 1989. Wasano, T., et al. Design Principles and Configuration of CTRON. Proc. 1987 Fall Joint Comp. Conf., pp. 159-166. Jim Mooney Dept. of Stat. & Computer Science (304) 293-3607 West Virginia University Morgantown, WV 26506 INTERNET: jdm@a.cs.wvu.wvnet.edu