gandalf@pro-electric.cts.com (Ken Hollis) (03/07/91)
Greetings and Salutations:
In response to the questions about the new GPC's (General Purpose
Computers) :
AP101S (New GPC) AP101B (Old GPC)
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B-1B Bomber Avionics (AP101F Modified) 1969 Aircraft Avionics
CPU & IOP (I/O Processor) in 1 box CPU & IOP in two boxes
560 Watts 780 Watts
64 Lbs. 117 Lbs.
CMOS 256 K Full Words Core 104 K Full Words
Half Word: 16 Data Bits 16 Data Bits
6 Error Detect&Correct 1 Parity Bit
3 Store Protect 1 Store Protect
>1000 K Operations Per Second 420 K Operations Per Second
Mean Time Between Fail Design 6000 Hrs 5250 Hours
Outlook 10000 Hrs MTBF
Currently 20000 Hrs MTBF
Space Hardened Higher Density IC's Space Hard Low Density IC's
AP101S microcode (8K X 72 PROM) has been modified so that instructions are
the same as the AP101B instructions (i.e. machine code compatible). There
is no "CPU" per se as there is in a home computer (i.e a Motorola 68040, or
a Intel 80486). It is a bit sliced, 6 stage pipelined architecture
(instruction address translate, instruction fetch, instruction decode,
operand address translate, operand fetch, instruction execute) in the same
vein as the IBM 360/370. The AP-101S central processor unit is optimized
for both MMP and MIL-STD-1750A Notice 2 architectures (the 1750A
architecture is not implemented in the standard AP-101S configuration, the
AP-101SG/1750 is a special ground based development configuration that
implements the 1750A architecture) and is comprised of the following 6
functional units:
Instruction unit
Effective address unit
Execution unit
Fractional data flow
Exponential data flow
Sequencer
These units are organized to execute instructions in a pipeline fashion
designed to provide results at a rate of one per machine cycle (250 ns)
when operating on simple instruction (with the pipe full).
The IOP functions as a programmable, time shared processor that transmits
and receives Shuttle Orbiter subsystems data under control of the CPU.
The SRAM is completely battery backed up. The SRAM is not non-volatile,
unlike the old core memory which was non-volatile.
Static Random Access Memory (SRAM) does not require a refresh, while Dynamic
RAM (DRAM) does. They both require power to maintain memory.
Ken Hollis
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