leichterj@rani.DEC (02/16/85)
In a recent note to a wide distribution:
Newsgroups: net.bugs.2bsd,net.bugs.4bsd,net.bugs.usg,net.bugs.uucp,
net.bugs.v7,net.unix-wizards
Henry Spencer writes:
Actually, a friend who got one of the first 780's outside DEC,
and had DEC people working with them for a while getting it
running, mentioned one other thing that compatibility mode
doesn't support: the MARK instruction. This omission is (I
believe) undocumented, but it's not surprising that nobody has
noticed the absence of the most useless instruction ever added
to the 11...
A minute or so with the documentation - in my case, the 1981 edition of
the VAX Architecture Handbook - reveals Table 17-3 - "Compatibility Mode
Reserved Instructions" - which lists those PDP-11 instructions that fault
to native mode (i.e., are not implemented by the hardware). MARK is right
in the middle of the list.
Given the usual high quality of Henry's writing, I was rather surprised to
see him "shooting from the hit" on something so easy to check.
-- Jerry
PS: For the curious, here's the complete list of "unimplemented" PDP-11
instructions:
The following cause reserved instruction faults to native mode:
HALT, WAIT, RESET, MFPT, SPL, MARK, CSM, MTPS, MFPS,
all FIS and FP11 floating point instructions, and all
"extended" instructions (these were user-microcoded on
the 11/60; I don't think any other -11 ever implemented
them).
The following cause traps to native mode:
BPT, IOT, EMT, TRAP
On VMS, and probably in the Unix compat package, the traps are simulated (by
simple munging with the stored PC) and the FP11 instructions are emulated by
executing the corresponding native instructions (the representations are
identical). (The FIS floating point instructions were only used on the
PDP-11/40; they are long obsolete.) The remaining instructions are mainly of
interest to OS implementers (e.g., WAIT) or are part of non-implemented PDP-11
features (e.g., MFPS - Move From Previous Space).
Non-implemented PDP-11 features include:
- Modes other than user; hence, alternate register sets;
- I/D space;
- Access to internal processor registers;
- Direct access to trap/interrupt vectors and I/O devices (though
the native mode support routines can map the I/O registers
into the compatibility mode space. However, many newer
devices require longword access to their registers, so the
compatibility mode code can't access them effectively any-
way.)
- Interrupt servicing;
- Stack overflow protection in the hardware.
There is also a difference in the granularity of the memory mapping hardware.henry@utzoo.UUCP (Henry Spencer) (02/22/85)
> A minute or so with the documentation - in my case, the 1981 edition of > the VAX Architecture Handbook - reveals Table 17-3 - "Compatibility Mode > Reserved Instructions" - which lists those PDP-11 instructions that fault > to native mode (i.e., are not implemented by the hardware). MARK is right > in the middle of the list. > > Given the usual high quality of Henry's writing, I was rather surprised to > see him "shooting from the hit" on something so easy to check. It's easy to check only if you happen to have a VAX, or at least VAX documentation, handy. Fortunately, I don't. (If you think you detect some anti-VAX bias... you're right.) My friend claimed that the absence of MARK was undocumented; he was probably right at the time. -- Henry Spencer @ U of Toronto Zoology {allegra,ihnp4,linus,decvax}!utzoo!henry
ron@BRL-TGR (Ron Natalie) (02/25/85)
The MARK instruction is listed as a reserved instruction in my March 1981 dated architecture book. -Ron