shovic@ui3.UUCP (John C. Shovic) (12/15/86)
SUPERCOMPUTING COURSE
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Department of Electrical Engineering
University of Idaho
Available nationally on videotape (spring semester):
1 - To instructors as a course they can offer and;
2 - To graduate students for credit.
Can be offered or taken as:
1 - A one hour seminar course or;
2 - A three hour research project course including use of machines
such as a CRAY X-MP/48, and Intel iPSC and the Massively Parallel
Processor.
Course Description and Outline ... attached
Additional Information:
Registration: Cathy Merickel, Engineering Outreach, University of
Idaho (208) 885-6373.
Course Content: Howard Demuth, Electrical Engineering Department,
University of Idaho (208) 885-7561 or Joe Hicklin,
Electrical Engineering Department, University of
Idaho (208) 885-7888.
Questions and comments on course content or organization are welcome.
EE 504 - SUPERCOMPUTING
This course gives a current view of parallel processing and
supercomputing. Commercial supercomputer architectures and various computing
applications will be reviewed. Research topics in parallel architectures, and
parallel programming and algorithms will be discussed. Various topics will be
presented by speakers from industry, government, and other universities.
This course may be taken as:
1 - EE 504 (1 cr) A one hour seminar with a midterm and final
exam or as;
2 - EE 504 (3 cr) A three hour course including a substantive
research project in parallel processing. Students will get to use various supercomputers, such as a CRAY X-MP/48, and
Intel iPSC, and the Massively Parallel Processor. (Off
campus students can access this equipment through a terminal and a modem.)
Prerequisite:
1 - Computer architecture course.
2 - Skills in at least two computer languages such as Pascal,
LISP, or FORTRAN.
Instructor:
Howard B. Demuth, Professor, Electrical Engineering.
Textbook:
Computer Architecture and Parallel Processing, by K. Hwang and
F. Briggs, McGraw-Hill.
Copies of lecture notes and transparencies will be available.
SUPERCOMPUTING
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I. Introduction
Progress in computing speeds
Economics
Applications
Present State
II. Background
2.1 Architecture
von Neumann Architecture
Parallelism in Central Processors
Overlapped CPU and I/O
Pipelining
Vectorization
Array Processors
Multiprocessor Systems
Interconnection Networks
Systolic Arrays
Memory Organization
2.2 Programming
Vectorization of Programs
Languages with Parallel Features
Language Design for Parallel Operation
Language/Architecture Relationships
2.3 Implementation Technology
Integrated Circuits
Computer Aided Design
Examples of VLSI Computer Design
Memory
2.4 System Considerations
Design Balance
Speed Measurement
Figures of Merit
Classification Schemes
2.5 Computer Networks
ARPAnet
BITnet
TELEnet
NSFnet
III. Computers of Historical Interest
Illiac IV
AP-120B
IBM 3838
Star-100
TI-ASC
C.mmp
Denelcor HEP
IV. Commerical Machines
Cray 2, Cray X-MP
Floating Point Systems FPS T
ETA 10
IBM 3084 Qx (+FPS 264s, FPS 164s)
CDC CYBER 205
Fujitsu VP-200
Hitachi 5810/20
NEC SX-2
Intel iPSC
Scientific Computer Systems SCS 40
Bolt, Beranek and Newman Butterfly Parallel Processor
Connection Machine
V. Research Architectures
Massively Parallel Processor (MPP)
NYU Ultracomputer
Cedar
Texas Reconfigurable Array Computer (TRAC)
Dataflow Machines
Redeuced Instruction Set Computers
Tree Machines
VI. Research Topics
Parallel Algorithms
Parallel Language/Architecture Relationship
Dynamic Logic
Cellular Automata
Parallel Inference Machines
Knowledge Based Systems
Silicon (Architecture) Compilers
Accelerators
Custom Architectures
VII. Applications
Aircraft Design
Biochemistry
Fluids and Plasmas
Geophysics
Image Processing
Molecular Modeling
Non-linear Dynamics
Optimization
VIII. Supercomputing Centers ... Research Speaker Sources
Supercomputing Research Centers
National Supercomputing Center
National Laboratories
IX. Future
Parallelism
Technology
Human Interfaces
Economics and Marketing
Impact on Society