sater@cs.vu.nl (Hans van Staveren) (01/04/88)
I recently asked whether anyone knew the programming info for the
Western Digital Ethercard Plus. Since then I found out that this card
is more commonly known as the WD8003E, and after much shouting at suppliers
I even got the documentation.
Since several people asked me to send the info, I post here the include
files for the WD8003E and for the NatSemi controller chip on that board.
Note that these are typed in from the documentation, but not tested yet.
But now..
Western Digital claims in the documentation that there Globally Assigned Address
Block, or most significant 24 bits of Ether address is C0:00:00, but are a bit
fuzzy about it.
Did they make this up or have they properly acquired it from Xerox?
Best wishes for '88 anyone.
: This is a shar archive. Extract with sh, not csh.
: This archive ends with exit, so do not worry about trailing junk.
echo 'Extracting etherplus.h'
sed 's/^X//' > etherplus.h << '+ END-OF-FILE etherplus.h'
X/*
X * Western Digital Ethercard Plus, or WD8003E card
X *
X * This information seems to be guarded like the crown jewels
X */
X
Xstruct eplusreg {
X char epl_ctlstatus; /* Control(write) and status(read) */
X char epl_res1[7];
X char epl_ea5; /* Least significant eaddr byte */
X char epl_ea4;
X char epl_ea3;
X char epl_ea2;
X char epl_ea1;
X char epl_ea0; /* Most significant eaddr byte */
X char epl_res2;
X char epl_chksum; /* sum from epl_ea5 upto here is 0 */
X dp8390 epl_dp8390; /* NatSemi chip */
X};
X
X/* Bits in epl_ctlstatus */
X
X#define CTL_RESET 0x80 /* Software Reset */
X#define CTL_MENABLE 0x40 /* Memory Enable */
X#define CTL_MEMADDR 0x3F /* Bits SA18-SA13, SA19 implicit 1 */
X
X#define STA_IIJ 0x7 /* Interrupt Indication Jumpers */
+ END-OF-FILE etherplus.h
chmod 'u=rw,g=r,o=r' 'etherplus.h'
echo 'SENT: -rw-r--r-- 1 sater 823 Jan 4 10:25 etherplus.h'
echo -n 'RCVD: '
/bin/ls -l etherplus.h
echo 'Extracting dp8390.h'
sed 's/^X//' > dp8390.h << '+ END-OF-FILE dp8390.h'
X/*
X * National Semiconductor DP8390 Network Interface Controller
X */
X
Xtypedef
Xunion dp8390reg {
X struct pg0rd { /* Page 0, for reading ------------- */
X char dp_cr; /* Read side of Command Register */
X char dp_clda0; /* Current Local Dma Address 0 */
X char dp_clda1; /* Current Local Dma Address 1 */
X char dp_bnry; /* Boundary Pointer */
X char dp_tsr; /* Transmit Status Register */
X char dp_ncr; /* Number of Collisions Register */
X char dp_fifo; /* Fifo ?? */
X char dp_isr; /* Interrupt Status Register */
X char dp_crda0; /* Current Remote Dma Address 0 */
X char dp_crda1; /* Current Remote Dma Address 1 */
X char dp_dum1; /* unused */
X char dp_dum2; /* unused */
X char dp_rsr; /* Receive Status Register */
X char dp_cntr0; /* Tally Counter 0 */
X char dp_cntr1; /* Tally Counter 1 */
X char dp_cntr2; /* Tally Counter 2 */
X } dp_pg0rd;
X struct pg0wr { /* Page 0, for writing ------------- */
X char dp_cr; /* Write side of Command Register */
X char dp_pstart; /* Page Start Register */
X char dp_pstop; /* Page Stop Register */
X char dp_bnry; /* Boundary Pointer */
X char dp_tpsr; /* Transmit Page Start Register */
X char dp_tbcr0; /* Transmit Byte Count Register 0 */
X char dp_tbcr1; /* Transmit Byte Count Register 1 */
X char dp_isr; /* Interrupt Status Register */
X char dp_rsar0; /* Remote Start Address Register 0 */
X char dp_rsar1; /* Remote Start Address Register 1 */
X char dp_rbcr0; /* Remote Byte Count Register 0 */
X char dp_rbcr1; /* Remote Byte Count Register 1 */
X char dp_rcr; /* Receive Configuration Register */
X char dp_tcr; /* Transmit Configuration Register */
X char dp_dcr; /* Data Configuration Register */
X char dp_imr; /* Interrupt Mask Register */
X } dp_pg0wr;
X struct pg1rdwr { /* Page 1, read/write -------------- */
X char dp_cr; /* Command Register */
X char dp_par0; /* Physical Address Register 0 */
X char dp_par1; /* Physical Address Register 1 */
X char dp_par2; /* Physical Address Register 2 */
X char dp_par3; /* Physical Address Register 3 */
X char dp_par4; /* Physical Address Register 4 */
X char dp_par5; /* Physical Address Register 5 */
X char dp_curr; /* Current Page Register */
X char dp_mar0; /* Multicast Address Register 0 */
X char dp_mar1; /* Multicast Address Register 1 */
X char dp_mar2; /* Multicast Address Register 2 */
X char dp_mar3; /* Multicast Address Register 3 */
X char dp_mar4; /* Multicast Address Register 4 */
X char dp_mar5; /* Multicast Address Register 5 */
X char dp_mar6; /* Multicast Address Register 6 */
X char dp_mar7; /* Multicast Address Register 7 */
X } dp_pg1rdwr;
X} dp8390;
X
X/* Bits in dp_cr */
X
X#define CR_STP 0x01 /* Stop: software reset */
X#define CR_STA 0x02 /* Start: activate NIC */
X#define CR_TXP 0x04 /* Transmit Packet */
X#define CR_DMA 0x38 /* Mask for DMA control */
X# define CR_DM_NOP 0x00 /* DMA: No Operation */
X# define CR_DM_RR 0x08 /* DMA: Remote Read */
X# define CR_DM_RW 0x10 /* DMA: Remote Write */
X# define CR_DM_SP 0x18 /* DMA: Send Packet */
X# define CR_DM_ABORT 0x20 /* DMA: Abort Remote DMA Operation */
X#define CR_PS 0xC0 /* Mask for Page Select */
X# define CR_PS_P0 0x00 /* Register Page 0 */
X# define CR_PS_P1 0x40 /* Register Page 1 */
X# define CR_PS_T0 0x80 /* Test Mode Register Map ?? */
X# define CR_SP_T1 0xC0 /* Test Mode Register Map ?? */
X
X/* Bits in dp_isr */
X
X#define ISR_PRX 0x01 /* Packet Received with no errors */
X#define ISR_PTX 0x02 /* Packet Transmitted with no errors */
X#define ISR_RXE 0x04 /* Receive Error */
X#define ISR_TXE 0x08 /* Transmit Error */
X#define ISR_OVW 0x10 /* Overwrite Warning */
X#define ISR_CNT 0x20 /* Counter Overflow */
X#define ISR_RDC 0x40 /* Remote DMA Complete */
X#define ISR_RST 0x80 /* Reset Status */
X
X/* Bits in dp_imr */
X
X#define IMR_PRXE 0x01 /* Packet Received iEnable */
X#define IMR_PTXE 0x02 /* Packet Transmitted iEnable */
X#define IMR_RXEE 0x04 /* Receive Error iEnable */
X#define IMR_TXEE 0x08 /* Transmit Error iEnable */
X#define IMR_OVWE 0x10 /* Overwrite Warning iEnable */
X#define IMR_CNTE 0x20 /* Counter Overflow iEnable */
X#define IMR_RDCE 0x40 /* DMA Complete iEnable */
X
X/* Bits in dp_dcr */
X
X#define DCR_WTS 0x01 /* Word Transfer Select */
X# define DCR_BYTEWIDE 0x00 /* WTS: byte wide transfers */
X# define DCR_WORDWIDE 0x01 /* WTS: word wide transfers */
X#define DCR_BOS 0x02 /* Byte Order Select */
X# define DCR_LTLENDIAN 0x00 /* BOS: Little Endian */
X# define DCR_BIGENDIAN 0x02 /* BOS: Big Endian */
X#define DCR_LAS 0x04 /* Long Address Select */
X#define DCR_BMS 0x08 /* Burst Mode Select */
X#define DCR_AR 0x10 /* Autoinitialize Remote */
X#define DCR_FTS 0x60 /* Fifo Threshold Select */
X# define DCR_2BYTES 0x00 /* 2 bytes */
X# define DCR_4BYTES 0x40 /* 4 bytes */
X# define DCR_8BYTES 0x20 /* 8 bytes */
X# define DCR_12BYTES 0x60 /* 12 bytes */
X
X/* Bits in dp_tcr */
X
X#define TCR_CRC 0x01 /* Inhibit CRC */
X#define TCR_ELC 0x06 /* Encoded Loopback Control */
X# define TCR_NORMAL 0x00 /* ELC: Normal Operation */
X# define TCR_INTERNAL 0x02 /* ELC: Internal Loopback */
X# define TCR_0EXTERNAL 0x04 /* ELC: External Loopback LPBK=0 */
X# define TCR_1EXTERNAL 0x06 /* ELC: External Loopback LPBK=1 */
X#define TCR_ATD 0x08 /* Auto Transmit */
X#define TCR_OFST 0x10 /* Collision Offset Enable (be nice) */
X
X/* Bits in dp_tsr */
X
X#define TSR_PTX 0x01 /* Packet Transmitted (without error)*/
X#define TSR_DFR 0x02 /* Transmit Deferred */
X#define TSR_COL 0x04 /* Transmit Collided */
X#define TSR_ABT 0x08 /* Transmit Aborted */
X#define TSR_CRS 0x10 /* Carrier Sense Lost */
X#define TSR_FU 0x20 /* Fifo Underrun */
X#define TSR_CDH 0x40 /* CD Heartbeat */
X#define TSR_OWC 0x80 /* Out of Window Collision */
X
X/* Bits in tp_rcr */
X
X#define RCR_SEP 0x01 /* Save Errored Packets */
X#define RCR_AR 0x02 /* Accept Runt Packets */
X#define RCR_AB 0x04 /* Accept Broadcast */
X#define RCR_AM 0x08 /* Accept Multicast */
X#define RCR_PRO 0x10 /* Physical Promiscuous */
X#define RCR_MON 0x20 /* Monitor Mode */
X
X/* Bits in dp_rsr */
X
X#define RSR_PRX 0x01 /* Packet Received Intact */
X#define RSR_CRC 0x02 /* CRC Error */
X#define RSR_FAE 0x04 /* Frame Alignment Error */
X#define RSR_FO 0x08 /* FIFO Overrun */
X#define RSR_MPA 0x10 /* Missed Packet */
X#define RSR_PHY 0x20 /* Multicast Address Match !! */
X#define RSR_DIS 0x40 /* Receiver Disabled */
X
X
Xstruct rcvdpacket {
X char rp_status; /* Copy of rsr */
X char rp_next; /* Pointer to next packet */
X char rp_rbcl; /* Receive Byte Count Low */
X char rp_rbch; /* Receive Byte Count High */
X char rp_packet[252]; /* Packet, may be larger */
X};
+ END-OF-FILE dp8390.h
chmod 'u=rw,g=r,o=r' 'dp8390.h'
echo 'SENT: -rw-r--r-- 1 sater 8099 Jan 4 10:15 dp8390.h'
echo -n 'RCVD: '
/bin/ls -l dp8390.h
exit 0