kapoor@wuee1.wustl.edu (Sanjay Kapoor) (12/15/90)
I have a couple a questions related to the SUPERNET chip set. Q) Given that SUPERNET does not impose a restriction on the response time of the interrupt latencies, what are the response times generally preffered? Of course it does depend on the interrupt priorities, worst case traffic patterns of frame arrival etc. Some real numbers is what I am looking for. Also in terms of performance, is it a good idea to run higher layer protocols and do SUPERNET housekeeping within the same chip? Higher layer protocols like say TCP/IP etc? This is because besides DPC, and Node processor, the third DMA channel that RBC services is a chip that processes only the data frames. All control frames are routed to the node processor. Suggestions/advice/Solutions are all greatly welcome. Thanks -Sanjay Kapoor kapoor@wuee1.wustl.edu
my@dtg.nsc.com (Michael Yip) (12/15/90)
kapoor@wuee1.wustl.edu (Sanjay Kapoor) writes: >I have a couple a questions related to the SUPERNET chip set. Good, at least someone is looking at FDDI. Finally. I don't know muct about the Supernet chipset but let me try ... (I just wonder if people from AMD can ask the questions ... :-) >Q) Given that SUPERNET does not impose a restriction on the response time of >the interrupt latencies, what are the response times generally preffered? >Of course it does depend on the interrupt priorities, worst case traffic >patterns of frame arrival etc. Some real numbers is what I am looking for. I am not sure what the "response time of the interrupt latencies" means. But let me assume you ask the question this way: "When the station receive the frame, how long can I wait until I grant the bus to the chipset so that the chipset can transfer content of the frame to memory?" Well, that depends on a few factors. Data bus width, on chip (or off chip) FIFO length, and transfer efficency. Let's assume a data bus width of 32 bits (4 bytes), a FIFO of 256 32-bits words. Also each burst of memory transfer will have 2 cycle overhead (25MHz or 40ns cycle), and 2 cycle for each word and 8 words max for each bus transfer transaction. 256 words = 256x4 bytes = 1K bytes = 1K Byte x 80ns/byte = 82 usec which means that if somehow data keeps coming in, then the on chip FIFO will get overflowed in 82usec if the Bus Request is not service within 82usec then the frame is "losted"! This will happen when the station is receiving a FDDI frame with max frame size (4500 bytes) and the system bus is too busy. That looks pretty bad, huh? Well, on the other hand, if the request is also serviced, then one max bus transfer transaction is just 2 + 2 * 8 cycles => 40ns * 18 cycles => 720ns. And compare that figure to the amount of time the FDDI network takes to deliver the data (8 words * 4 words/byte * 80ns/byte = 2560ns), that means the network is using 28% of the bus at most! And the network "never" flood a station constainly ('cause of preamble, frame overhead, token, not all broadcast frame ...). So don't worry too much, if just do some calculation before you actually sit down to design an FDDI card. But the way, 82usec bus respond time is quite a lot too ask on some bus architecture (say VME?) and 82usec may be very reasonable on other buses. >Also in terms of performance, is it a good idea to run higher layer protocols >and do SUPERNET housekeeping within the same chip? Higher layer protocols like >say TCP/IP etc? Depends on what performance you are talking about, as far as a computer system is concern, I think that the Node processor should do everything and let the real system processor do number cunching. Therefore, protocol processing, in general, should be done by other processors (say the Node processors). However, that might be different if you are talking about router or bridge. (After all those systems are doing protocol processing to earn their $) >This is because besides DPC, and Node processor, the third DMA channel that >RBC services is a chip that processes only the data frames. All control >frames are routed to the node processor. Not sure what you mean by "control frames". Are you refering to the FDDI draft Station Management (SMT) type of frames? Well, if you are on a "cheap" system, you might want to have your system processor do the SMT frame processing. SMT frames, hopefully, do not happen too often. The standard requires at least one SMT frame (NIF, SIF) to be transmitted every 30 secs, that is not too much to ask for in a station that use FDDI, isn't it? SMT only kicks into action if "something happened" on the network so it is/was designed not to use up too much processing time. If the chipset is reasonablely implemented, SMT will not be a high overhead on the system. But, I still think that a Node processor is a good idea even on cheap and small systems. >Suggestions/advice/Solutions are all greatly welcome. Well, I typed a lot but I don't even know if I am answering the questions ;) Have fun and send me mail if you need any help. -- Mike Yip my@dtg.nsc.com PS: National Semiconductor Corp also manufactor FDDI chipset too. Give them a call to compare between the two chipsets' design. Call 408 721-3848. Sorry, this sounds like marketing.
ananth@hpindda.cup.hp.com (AP Anantharaman) (12/18/90)
/ hpindda:comp.dcom.lans / kapoor@wuee1.wustl.edu (Sanjay Kapoor) / 2:27 pm Dec 14, 1990 / What is this SUPERNET chipset ? Who manufactures them ? Are there any FDDI cards made with this chipset ? ananth@hpda --------------------------------------------------------------------------- I have a couple a questions related to the SUPERNET chip set. Q) Given that SUPERNET does not impose a restriction on the response time of the interrupt latencies, what are the response times generally preffered? Of course it does depend on the interrupt priorities, worst case traffic patterns of frame arrival etc. Some real numbers is what I am looking for. Also in terms of performance, is it a good idea to run higher layer protocols and do SUPERNET housekeeping within the same chip? Higher layer protocols like say TCP/IP etc? This is because besides DPC, and Node processor, the third DMA channel that RBC services is a chip that processes only the data frames. All control frames are routed to the node processor. Suggestions/advice/Solutions are all greatly welcome. Thanks -Sanjay Kapoor kapoor@wuee1.wustl.edu ----------
my@dtg.nsc.com (Michael Yip) (12/19/90)
In article <3530009@hpindda.cup.hp.com> ananth@hpindda.cup.hp.com (AP Anantharaman) writes: >What is this SUPERNET chipset ? Who manufactures them ? Are there any FDDI >cards made with this chipset ? Well, SUPERNET chipset is a FDDI PHY/MAC/SYS implementation by AMD. The DP83200 chipset is another FDDI PHY/MAC/SYS implementation by National Semi AT&T also make a PHY layer only chip. -- Mike my@dtg.nsc.com