paulc@jetsun.weitek.COM (Paul Chai) (05/08/91)
If there are any kind souls out there fluent in ethernet s/w drivers
in particular with the AMD LANCE chip, i need help with the following
questions??? Any help would be highly appreciated!!
Questions:
1. Is it reasonable/doable to insist memory buffers start on a quadword/word
address rather than any arbitrary byte address??? The receive/transmit
descriptor rings are after all on quadword address boundary.
2. ON ethernet Read/Write DMA transfers, you have the following data
pattern "....,addr,data,addr,data,.....,addr,data" . Is it safe to assume
in a contiguous transfer ie. HOLD- continously asserted that all the
addresses are consecutive eg. 10,12,14,16,...etc??? This would enable
one to only need to buffer the first address.
3. What is the appropriate way of draining data to memory during a DMA
write transfer??? Wait for a Lance interrupt to do it ???
thank you all....
paulcching@brahms.amd.com (Mike Ching) (05/11/91)
In article <1991May8.165555.16300@jetsun.weitek.COM> paulc@jetsun.WEITEK.COM (Paul Chai) writes: >If there are any kind souls out there fluent in ethernet s/w drivers >in particular with the AMD LANCE chip, i need help with the following >questions??? Any help would be highly appreciated!! >Questions: > 1. Is it reasonable/doable to insist memory buffers start on a quadword/word > address rather than any arbitrary byte address??? The receive/transmit > descriptor rings are after all on quadword address boundary. It is undesirable to insist that memory buffers start on quadword addresses since it would probably require a data copy to comply with the requirement. Word alignment is less of a problem since headers are an even number of bytes. The alignment requirement of the descriptor rings is not much of a restriction since control structures will rarely cause this copying overhead. > 2. ON ethernet Read/Write DMA transfers, you have the following data > pattern "....,addr,data,addr,data,.....,addr,data" . Is it safe to assume > in a contiguous transfer ie. HOLD- continously asserted that all the > addresses are consecutive eg. 10,12,14,16,...etc??? This would enable > one to only need to buffer the first address. Most existing DMA controllers including the one in the LANCE do transfers only to consecutive addresses. However software does not have access to the transactions on the memory bus so I'm not sure how relevant this is. > 3. What is the appropriate way of draining data to memory during a DMA > write transfer??? Wait for a Lance interrupt to do it ??? I don't understand this question. The LANCE writes the data into memory. There is no need to drain anything. Mike Ching AMD Field Applications