feustel@well.sf.ca.us (David Alan Feustel) (11/17/90)
386 dma device drivers operating in protected mode are complicated and
slowed down by the need to convert task virtual addresses to physical
addresses for io transfers. This is really not necessary if the device
controller has bus mastering capability. A device controller with bus
mastering capability armed with pointers to the GDT, LDT and page table
directory can use its bus mastering capability to "snoop" through the
386 memory and can use the information gained to load its own on-board
address translation table so that task i/o addresses are converted to
the correct physical addresses on the fly during bus mastered dma.
All that is necessary for this to work is for the addressed segment to
be present in memory and for the affected pages to be present and locked
in memory by the operating system for the duration of the i/o transfer.
The advantage of this scheme is that with it i/o operations in paged
operating systems no longer have to be decomposed into operations on 4k
blocks. The 4k block problem is purportedly the reason for the ~60%
performance degradation of the IBM PS/2 SCSI controller when operating
in protected mode.
Another advantage is that dma i/o can be performed from priviledge level
3 tasks without operating system intervention if the controller has
current GDT/LDT/Page table information, the task has i/o permission
for the appropriate i/o ports and no interrupt handling is needed.
Controllers supporting this mechanism would not require operating system
dependent drivers. In addition, their thruput would be substantially better
since OS overhead associated with i/o transfers would be greatly reduced.
Ideally, all of the logic for this address translation would be put into
a single bus interface glue chip for use with i/o subsystems already
designed to work with physical addresses.
--
Dave Feustel, 1930 Curdes Ave, Fort Wayne, IN 46805-2710 (219)-482-9631
EMAIL: feustel@well.sf.ca.us {ucbvax,apple,hplabs,pacbell}!well!feustel
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