tnixon@hayes.uucp (01/18/91)
In a recent mailing, the Special Rapporteur for V.fast in CCITT Study Group XVII gave the group a list of papers expected to be presented at the upcoming meeting (6-8 Feb 1991 in Ft. Lauderdale). The abstracts of the papers give you an idea of the kind of proposals that are being presented. I thought some of you might be interested in them. (1) IBM/Gottfried Ungerboeck -- Two papers are in process: (a) A new 2-dimensional 64-state non-linear, rotationally-invariant trellis coding scheme, which has the feature of being implemented with varying degrees of complexity and providing coding gain ranging from parity with the 8-state trellis coding as in V.32 to an additional improvement of up to 1.2dB; (b) a candidate startup procedure using interleaved tones from opposite ends of the channel for channel measurement and moderate (narrow-band QPSK @ 300 baud) modulation of interleaved centrally-located tones for data communications without the need of echo cancellation. (2) Telebit/John Bingham -- Two papers are in process: (a) Echo cancellation, both near and far end, for multicarrier signalling combining advantages of data-driven adaptation and signal-driven echo emulation. In order to allow adaption in the frequency domain, the echo part of a received signal is made to appear cyclin by tail subtraction and cyclic echo construction. The paper also describes methods of compensating for frequency offset in a far echo, and for fast initial training of the canceller in a half-duplex mode; (b) a draft proposal for a full-duplex multicarrier modem that operates at speeds up to 24,000 bits per second. (3) Codex/David Forney -- Two papers are in process: (a) A single-carrier modem for V.fast: description and test results; presents a description of and test results for an implementation of a single-carrier high-speed duplex two-wire modem at data rates up to 24,000 bits per second.; (b) originally drafted by Codex and now sources by Codex, General Datacomm, AT&T, Octocom, Hayes, and others, entitled Single-Carrier Modulation for V.fast; discusses the question of single-carrier vs. multicarrier modulation, and recommends focusing on single-carrier modulation for V.fast. (4) British Telecom/John Brownlie -- paper will address operating procedures for V.fast. The aspects considered will include start-up times, automoding, training signals, rate signalling procedures, bandwidth estimation, and symbol-rate changing. (5) Intelligent Modem Corporation/Laura Preece -- paper will discuss an additional approach to multicarrier modulation, including solutions for cancellation of both near- and far-end echoes, and considerations for peak-to-average ratio and system delay. The meeting will be lively, filled with facsinating discussions and arguments over the various proposals and papers. Wish you could all be there! It will certainly be interesting to finally see Telebit's proposal for echo cancellation in multicarrier modulation and Codex's proposal for single-carrier 24000 bit/s modulation (that's synchronous bit rate, without data compression, folks). -- Toby Nixon, Principal Engineer | Voice +1-404-449-8791 Telex 151243420 Hayes Microcomputer Products Inc. | Fax +1-404-447-0178 CIS 70271,404 P.O. Box 105203 | UUCP uunet!hayes!tnixon AT&T !tnixon Atlanta, Georgia 30348 USA | Internet hayes!tnixon@uunet.uu.net
casey@gauss.llnl.gov (Casey Leedom) (01/19/91)
| From: tnixon@hayes.uucp (Toby Nixon) | | [[Abstracts of all sorts of interesting new modem technology proposals.]] | | The meeting will be lively, filled with fascinating discussions and | arguments over the various proposals and papers. Wish you could all be | there! It will certainly be interesting to finally see Telebit's | proposal for echo cancellation in multicarrier modulation and Codex's | proposal for single-carrier 24000 bit/s modulation (that's synchronous | bit rate, without data compression, folks). I wish I could be there too even though I wouldn't understand most of the hard core engineering and signal processing issues. (Just a software geek.) But two questions pop into my mind immediately: 1. My [naive] guess would be that multi-carrier technology would be a lot better than single-carrier because of multi-carrier's ability to adapt around bad spots in the frequency response spectrum. Since Hayes is arguing in favor of single-carrier technology can you give us a brief on what the arguments are in favor of each? 2. With 24Kbps, V.42bis could offer up to 96Kbps and may typically deliver 48Kbps. Obviously we'll want to run our interfaces near that 96Kbps in order to give V.42bis a chance to deliver all that it can. What kind of interfaces are we going to use that will operate at that rate? I don't think that we can expect to push that old war hound EIA-232 that far. Perhaps this will provide the impetuous for EIA-422 (or is it 423?) to start appearing as standard equipment in personal computers, terminals, etc. Are there interface chips that can operate at this speed and take most of the load off of the CPU? (DMA output and SILOed input.) Casey
tnixon@hayes.uucp (01/24/91)
In article <89753@lll-winken.LLNL.GOV>, casey@gauss.llnl.gov (Casey Leedom) writes: > 1. My [naive] guess would be that multi-carrier technology would > be a lot better than single-carrier because of multi-carrier's > ability to adapt around bad spots in the frequency response > spectrum. > > Since Hayes is arguing in favor of single-carrier technology > can you give us a brief on what the arguments are in favor > of each? First of all, it's pretty rare to have single tone or other impairment that affects a narrow range of frequencies. Very rare, in fact. Most impairments affect a wide range of frequencies. In a multicarrier modem, it makes sense to be able to adaptively "turn off" (or adjust the number of bits sent on) individual frequencies. In a single-carrier modem, narrow-band impairments don't have much impact, and are generally handled by the equalizer. > 2. With 24Kbps, V.42bis could offer up to 96Kbps and may typically > deliver 48Kbps. Obviously we'll want to run our interfaces > near that 96Kbps in order to give V.42bis a chance to deliver > all that it can. > > What kind of interfaces are we going to use that will operate at > that rate? I don't think that we can expect to push that old > war hound EIA-232 that far. Perhaps this will provide the > impetuous for EIA-422 (or is it 423?) to start appearing as > standard equipment in personal computers, terminals, etc. > Are there interface chips that can operate at this speed and > take most of the load off of the CPU? (DMA output and SILOed > input.) There are two EIA standard interfaces that are likely to be considered the choice for these higher speeds. First is EIA-562, which is "compatible" with EIA-232 (is an entirely unbalanced interface). Two connectors are defined for 562 now: a 9-pin connector (identical to the PC AT), EIA-574, and an 8-pin modular connectors, EIA-561. EIA-562 has the advantage of operating with only +5 volt supply, at up to 64000bps (but can be pushed higher). The best choice will probably be EIA-530. This uses the same 25- or 26-pin connector as EIA-232, but uses EIA-422 (balanced) circuits for signals that change quickly (data, clocks) and EIA-423 (unbalanced) circuits for signals that don't change as often (DTR, DCD, etc.) There are companies that have driver and receiver chips available which can be switched between 232 and 530 on the fly. 530 was designed so that drivers and receivers are in the same place as the most commonly-used 232 circuits. One example of a device which can take the load off the CPU for high-speed transfer is the Hayes Enhanced Serial Port (ESP). It has two 16550AFNs on it, plus an 8031 microcontroller. Both transmit and receive have 1K-byte FIFOs, and the 8031 supports direct DMA transfers to/from main memory. ESP current supports only up to 38400 bps, but I suspect Hayes will come up with a new version that supports higher speeds in the future [this is NOT a product announcement, folks!]. There are similar buffered devices from other companies, but most of them don't preserve backward compatibility with existing comm software (which ESP does). -- Toby -- Toby Nixon, Principal Engineer | Voice +1-404-449-8791 Telex 151243420 Hayes Microcomputer Products Inc. | Fax +1-404-447-0178 CIS 70271,404 P.O. Box 105203 | UUCP uunet!hayes!tnixon AT&T !tnixon Atlanta, Georgia 30348 USA | Internet hayes!tnixon@uunet.uu.net
root@zswamp.fidonet.org (Geoffrey Welsh) (01/27/91)
>From: tnixon@hayes.uucp >The best choice will probably be EIA-530. This uses the >same 25- or 26-pin connector as EIA-232, but uses EIA-422 (balanced) >circuits for signals that change quickly (data, clocks) and EIA-423 >(unbalanced) circuits for signals that don't change as often >(DTR, DCD, etc.) Do we really need a mongrel serial design? Is the cost of going whole-hog balanced that high that we can't afford the consistency? >One example of a device which can take the load off the CPU >for high-speed transfer is the Hayes Enhanced Serial Port (ESP). >It has two 16550AFNs on it, plus an 8031 microcontroller. Both >transmit and receive have 1K-byte FIFOs, and the 8031 supports direct >DMA transfers to/from main memory. Ah, I was wondering what those things were, thanks for the info. >There are similar buffered devices from >other companies, but most of them don't preserve backward >compatibility with existing comm software (which ESP does). Then I don't suppose that the ESP uses the 16550's DMA mode? -- UUCP: watmath!xenitec!zswamp!root | 602-66 Mooregate Crescent Internet: root@zswamp.fidonet.org | Kitchener, Ontario FidoNet: SYSOP, 1:221/171 | N2M 5E6 CANADA Data: (519) 742-8939 | (519) 741-9553 MC Hammer, n. Device used to ensure firm seating of MicroChannel boards Try our new Molson 'C' compiler... it specializes in 'case' statements!