cshouse@ritcv.UUCP (Computer Science House (CSH)) (07/06/86)
This article is in response to the "RISC: Myth and Reality" article published in this month's (July) UNIX World. Within this article, Fairchild's CLIPPER Module is classified as a CISC processor. This is dead WRONG! Fairchild's CLIPPER module: 1) has a completely hard-wired instruction set, 2) contains no micro-code and 3) utilizes a Load/Store architecture!!! In Omri Serlin's article, he uses CMU's six criteria for a RISC processor and has placed CLIPPER in the CISC group. It should be placed in the Semi-RISC group, if the CMU criteria is used! 1) The CLIPPER module has a completely hard-wired instruction set with 101 basic instructions and 67 MI ROM instructions which are just sequences of these basic hard-wired instructions. Due to the thruput requirements of the CLIPPER CPU, the CLIPPER design team determined no time would be left for decoding micro-code, so the CPU control was implemented as a hard-wired state machine. 2) The CLIPPER module has a MACRO Instruction (MI ROM) which contains sequences of hard-wired instructions. This is NOT micro-code!!! When an MI ROM instruction is encountered in the instruction stream, an instruction sequence is read from the MI ROM and is inserted into the DECODE and RESOURCE MANAGEMENT stage of the instruction pipeline! The input of this sequence into the instruction pipeline is maintained at the peak instruction rate of 1 clock cycle (30ns). At the end of the MI instruction sequence, the instruction stream is switched back to the Instruction Cache/Memory Management Unit (ICAMMU) instruction buffer. In addition, the MI ROM is equipped with its own internal register file to avoid saving and restoring the general purpose register files. Also, interrupt latency isn't affected during long sequences of these instructions, as some MI ROM instructions can be interrupted, such as the CMPC instruction (string compare). 3) And, the CLIPPER module is implemented as a load / store register to register instruction set. All non-memory instructions operate only on registers, and all memory reference instructions pass data between a single memory location and one register. Now, if computer system architectures were compared, as opposed to just theoretically comparing processors, the truth would be unveiled. The other processors mentioned in this article do NOT have the capability, once realized into an actual architecture, to acheive their "true" potential, as does Fairchild's CLIPPER. Let's see some discussion on these processors, as they can be realized into actual architectures. The CLIPPER Research Project is involved in the research and development of CLIPPER SHIP which is a high-end general purpose 32-bit super minicomputer based upon Fairchild Corporation's CLIPPER Module and the RIT 1.0 version of UNIX (a 4.2BSD UNIX port). --------------------------------------------------------------------------- CLIPPER Research Project Team Frank Giuffrida Computer Science House Paul Netzband Rochester Institute of Technology Steve Adams Rochester, NY 14623 Brad Werner (716) 475-3305 UUCP: seismo!rochester!ritcv!ritcsh!clipper