jcn@aplvax.UUCP (03/27/87)
I am working on a device driver for a dr11-w board connected to an NTDS interface board on a MicroVax II. In the process, I have come up with several questions that I thought some guru on the net might be able to answer. 1. I had thought that the dr11-w board was set at bus request level 5, but when the the board was probed at boot time, it reported the device was ipl 17. I then changed the br level on the board, and it still reported ipl 17. Does the standard probe routine for unibus devices (vector in r10 and ipl in r11) work for the Q-bus? 2. I talked with the DEC customer support, and they insisted that the priorities on the Q-bus were not determined by distributed arbitration (as on the MicroVax I Q-bus!) but are purely defined by card position on the bus (closer to the CPU board dictates higher device priority). (Distributed arbitration means that the priority levels are implemented on the board itself; in the case of two boards at the same br level, the closest to the CPU board wins.) If this is the case, if we wanted to protect a segment of kernel code from device interrupts, it would seem that either all device interrupts are disabled, or none are; further, which spl? function would then be used to disable them? 2. If the Q-bus on the MVII actually selects priority by distributed arbitration, then another question arises. On the Q-bus, bus request level 7 is the highest, and 4 is the lowest. Note that this is the opposite from the unibus, where br 7 is lower priority than br 4. So, it seems that a driver written for a device on a unibus needs to be ported very carefully to a Q-bus architecture. The spl? functions (spl0, spl1, spl4, spl5, spl6, spl7) would need to be different, or at least be interpreted differently. For example, on the unibus, spl5() would lock out interrupts priority 5 and *higher* interrupts. On the Q-bus, spl5() would lock out interrupts priority 5 and *lower* interrupts. Comments? 3. On the Vax 11/780 (Unibus), I looked at the expansion of the spl?() functions. As I would expect, they do the following: spl0() places a 0 in privileged register 0x12 (the IPL register) spl1() places a 1 in privileged register 0x12 (the IPL register) spl4() places a 0x14 in privileged register 0x12 (the IPL register) spl5() places a 0x15 in privileged register 0x12 (the IPL register) spl6() places a 0x16 in privileged register 0x12 (the IPL register) spl7() places a 0x17 in privileged register 0x12 (the IPL register) On the MVII (Q-bus), this is the what the the spl? functions do: spl0() places a 0 in privileged register 0x12 (the IPL register) spl1() places a 1 in privileged register 0x12 (the IPL register) spl4() places a 0x14 in privileged register 0x12 (the IPL register) spl5() places a 0x15 in privileged register 0x12 (the IPL register) spl6() places a 0x18 in privileged register 0x12 (the IPL register) spl7() places a 0x1f in privileged register 0x12 (the IPL register) Any comments on why spl6() and spl7() were changed in this way? Thanks. John Noble JHU/APL jcn@aplvax.arpa ...!mimsy!aplcen!aplvax!jcn