art@acc.arpa (07/29/87)
Chris, For your information... >Here is a short summary of these routines. Note that I speak only >for 4.[23]BSD, and for that matter, that I have never even read a >Unibus manual. I have been forced to learn how the hardware works >by reading software. (E.g., I still do not know exactly what a >buffered data path *does* and when one must be used.) The UNIBUS buffered data paths are essentially caches between the UNIBUS and the central system interconnects (SBI, CMI etc). The SBI in particular is most efficient when transferring 8 bytes to/from memory in a single SBI transaction. The direct data path maps the one or two byte UNIBUS transactions into an SBI transaction. This causes inefficient SBI use and causes the UNIBUS cycle to stall untill the SBI transaction finishes. The buffered data paths allow data to be quickly passed between the UNIBUS and the cache memory until an 8 byte SBI transaction is needed. This is why buffered data paths need to be "purged", to flush data out of the SBI cache into main memory, after a UNIBUS DMA transfer has finished. The buffered data paths also support the byte offset mechanism which allows word addressing UNIBUS devices to transfer to odd byte aligned VAX memory buffers. Art Berggreen art@acc.arpa ------