aburke@ogicse.cse.ogi.edu (Andrew Burke) (07/23/90)
Due to the overwhelming response... Here is the bibliography, as promised. There are notes associated with most entries. Please understand that these descriptions are meant not to completely define and classify the article, but just to give some idea what the paper is about. I have tried to be as accurate as possible, but please forgive (and correct!) me in advance for any misrepresentations. Andrew Burke aburke@cse.ogi.edu --cut here----cut here----cut here----cut here----cut here----cut here-- Annotated Bibliography [Abram 86] Greg D. Abram & Henry Fuchs, "VLSI Architectures for Computer Graphics," Advances in Computer Graphics I, (EUROGRAPHICS 1986), pp. 189-204. Good review of the work that has been done in this field, both in industry and academia. They classify Clark's Geometry Engine and Fuchs' Pixel-Planes as operating in image space, while Kedem and Cohen's work is in object space. Defines a general graphics computing model and how it has been implemented in various devices and their architectures. VLSI for line drawing, bit-blitting. VLSI for systems: TI's 4161 row-scan memory chip, Clark's Geometry Engine, NEC's 7220 raster fill and scan chip, TI's TMS9118. Also different VLSI architectures: Clark and Hannah's screen segmentation, the Pixel-Planes approach, Kedem's CSG machine, Cohen and Demetrescu's processor per polygon. [Agate 86] M. Agate, H.R. Finch, et. al. (University of Sussex), "A Multiple Application Graphics Integrated Circuit - MAGIC," Proceedings of European Computer Graphics Conference and Exhibition, The Computer Interface, 1986, pp. 67-77. The first MAGIC chip is outlined. This chip can be used in parallel to provide good performance. The chip is general purpose. They outline a system architecture and the operations of the chip. See also [Finch 87] for the MAGIC II chip. [Ajjanagadde 88] Venkatramana G. Ajjanagadde (University of Pennsylvania) & L. M. Patnaik (Indian Institute of Science), "Design and Performance Evaluation of a Systolic Architecture For Hidden Surface Removal," Computers & Graphics, vol. 12, no. 1, Pergamon Press Ltd., 1988, pp. 71-74. Using a systolic architecture, they discuss the implementation of a basic hidden surface algorithm and its performance (simulated). [Akeley 88] Kurt Akeley & Tom Jermoluk (Silicon Graphics), "High-Performance Polygon Rendering," Computer Graphics, vol. 22, no. 4, (Proc. SIGGRAPH '88), August 1988, pp. 239-246. An architecture for fast polygon rendering, used in a Silicon Graphics system. The graphics system is made up of 4 pipelined subsystems: geometry, scan conversion, raster, and display. Each subsystem is discussed in turn, and the performance is evaluated. [Akeley 89] Kurt Akeley (Silicon Graphics), "The Silicon Graphics 4D/240GTX Superworkstation," IEEE Computer Graphics and Applications, July 1989. Review of a new workstation's architecture and how it compares with other systems. Nice system of classification for graphic workstations; spends time discussing the compromises that have to be made to support certain operations. See also [Bell 88], [Borden 89]. [Akman 87] Varol Akman, Paul ten Hagen & Fons Kuijk (Centre for Mathematics and Computer Science, The Netherlands), "A Vector-like Architecture for Raster Graphics," Advances in Computer Graphics Hardware II, Record of Second Eurographics Workshop on Graphics Hardware, 1987, pp. 137-154. They offer a new view on graphics systems, and a architecture which supports a higher level primitive, which they call a "pattern representation." This primitive is a pattern consisting of a domain function and a color function. See also [Kuijk 87], [Hagen 86]. [Alliant 89] Alliant Product Literature, 1989 Discussion of graphics standards running on a parallel machine. [Apgar 88] Brian Apgar, Bret Bersack & Abraham Mammen (Stellar Computer), "A Display System for the Stellar Graphics Supercomputer Model GS1000," Computer Graphics, vol. 22, no. 4, (Proc. SIGGRAPH '88), August 1988, pp. 255-262. The display system of the Stellar machine is outlined. An interesting aspect is their use of tagged data to allow time dependent operations to be executed in the correct order. Comparisons are made with other systems. [ATT 88] AT&T Pixel Machines Product Literature, 1989 [Badouel 90] Didier Badouel, Kadi Bouatouch & Thierry Priol (University of Rennes, France), "Ray Tracing on Distributed Memory Parallel Computers: Strategies for distributing computations and data," Technical Report 508, Institut de Recherche en Informatique et Systemes Aleatoires (IRISA), January 1990. Good survey of various approaches to ray tracing on distributed memory parallel computers. Covers techniques to emulate global shared memory on a distributed computer. [Barton 86] Eric Barton (Meiko, UK), "Meiko's Computing Surface", Computer Graphics '86, Online Publications, Pinner, UK, 1986. How the Meiko Computing Surface came to be, how it can be used, and how it is organized. [Barton 88] Eric Barton (Meiko Ltd, UK), "Data Concurrency on the Meiko Computing Surface," Parallel Processing for Computer Vision and Display, International Conference, University of Leeds, UK, 12-15 January, 1988 The product, the uses, some problems, some solutions. [Baum 90] Daniel R. Baum & James M. Winget (Silicon Graphics), "Real Time Radiosity Through Parallel Processing and Hardware Acceleration," Computer Graphics, vol. 24, no. 2, March 1990 (Proceedings of the 1990 Symposium on Interactive 3D Graphics), pp. 67-75. As the title says, radiosity in real time (!), using progressive refinement on a multiprocessor workstation. They discuss load balancing and other performance issues. [Bell 88] C. Gordon Bell, Glen S. Miranker & Jonathan J. Rubinstein (Ardent Computer Company), "Supercomputing for One," IEEE Spectrum,, April 1988, pp. 46-50 "Graphics supercomputers are parallel multiprocessor systems. They have high speed integer processors and 64 bit vector processors like those used in supercomputers..." A good overview of the current work being being done to produce affordable graphics supercomputers, by Apollo, Stellar, Ardent and others. The basic systems are outlined, and their performance compared with real supercomputers. [Borden 89] Bruce S. Borden (Ardent Computer), "Graphic Processing on a Graphics Supercomputer," IEEE Computer Graphics and Applications, July 1989. Review of the architecture of a graphics supercomputer from Ardent. This system tries not to have lots of specialized graphics processors, but instead strives to use general purpose processing units, connected in parallel or pipelined. See also [Bell 88] and [Akeley 89]. [Caspary 88] E. Caspary & I.D. Scherson (University of California, Santa Barbara), "A Self-Balanced Parallel Ray Tracing Algorithm," Parallel Processing for Computer Vision and Display, International Conference, University of Leeds, UK, 12-15 January, 1988 They divide up the object space, assigning each area to different processors in a hypercube architecture. Each processor runs two processes: one to compute ray intersections with the bounding volumes, one to compute intersections with objects. Appears to load-balance well. [Chalmers 88] M. Chalmers (University of East Anglia, UK), "On The Design and Implementation of a Multiprocessor Ray Tracer," Parallel Processing for Computer Vision and Display, International Conference, University of Leeds, UK, 12-15 January, 1988 Problems with Occam, and how a parallel ray tracer might be built using a object-oriented language such as Actors. [Chang 81] P. Chang & Ramesh Jain (Wayne State University), "A Multi-Processor System for Hidden-Surface-Removal, " Computer Graphics, (Proc. SIGGRAPH '81), vol. 15, no. 4, December 1981, pp. 405-436. One of the early papers on how to parallelize Watkins' hidden surface algorithm. They physically divide up the screen into disjoint areas for different processors. They note that as more processors are added, clipping time begins to dominate. Good description of data structures used. [Chen 89] Shenchang Eric Chen (Cornell), A Progressive Radiosity Method and its Implementation in a Distributed Processing Environment, Masters Thesis, Program of Computer Graphics, Cornell University, Ithaca, NY, January 1989. One of the first published papers on parallelizing radiosity. Used a network of workstations. [Cheng 88] F. Cheng &Y.K. Yen (University of Kentucky), "A Parallel Line Clipping Algorithm and its Implementation," Parallel Processing for Computer Vision and Display, International Conference, University of Leeds, UK, 12-15 January, 1988 Extensions to Liang-Barsky algorithm, parallel-hardware geometry system (hardware & software). Only line clipping. [Cheng 89] Fuhua Cheng & Ardeshir Goshtasby (University of Kentucky), "A Parallel B-spline Surface Fitting Algorithm," ACM Transactions on Graphics, vol. 8, no. 1, January 1989. Support different surface types. Because surface fitting appears to be a O(nm) problem, attacking the problem in parallel can make b-splines more supportable. See also [Yang 87], [Schnieder 87]. [Clark 82] James H. Clark (Stanford University, Silicon Graphics), "The Geometry Engine: A VLSI Geometry System for Graphics," Computer Graphics, vol. 16, no. 3, (Proc. SIGGRAPH '82), July 1982, pp. 127-133. One of the more commercially successful developments in parallelism and graphics. Used in the Silicon Graphics IRIS system. He describes the different uses of the Geometry Engine, and how it can be pipelined. [Claussen 87] Ute Claussen (Eberhard-Karls Universitat Tubingen), "Parallel Subpixel Scanconversion," Advances in Computer Graphics Hardware II, Record of Second Eurographics Workshop on Graphics Hardware, 1987, pp. 155-166. An approach to solving the jagged edges problem when rasterizing polygons. They present a pipelined and a parallel system for doing the sampling, and determine that the parallel system is better. [Cleary 86] John G. Cleary, Brian M. Wyvill, Graham M. Birtwistle & Reddy Vatti (University of Calgary), "Multiprocessor Ray Tracing," Computer Graphics Forum 5, North-Holland Publishers, 1986, pp. 3-12. Good discussion on a parallel ray tracer built for a 3D array of processors, and limitations of ray tracers in vector architectures. No load balancing, and everything is simulated. [Cohen 85] Michael F. Cohen & Donald P. Greenberg (Cornell University), "The Hemi-Cube, A Radiosity Solution for Complex Environments," Computer Graphics, vol. 19, no. 3, (Proc. SIGGRAPH '85), July 1985, pp. 31-40. One of the early papers on radiosity. Introduces the use of the hemi-cube for form factor calculations. Doesn't mention parallelism, but its use is hinted at. [Crow 88] F. C Crow et. al. (Xerox PARC, Whitney/Demos), "3D Image Synthesis on the Connection Machine," Parallel Processing for Computer Vision and Display, International Conference, University of Leeds, UK, 12-15 January, 1988. Good description of the Connection Machine and it's advantages and limitations when used for graphics. Discussion of how to do general graphic operations (clipping, transforms, scan conversion, shading). [Curington 86] Ian J. Curington (Floating Point Systems), "Computer Graphics and Array Processors," Computer Graphics '86, Online Publications, Pinner, UK 1986. How Floating Point Systems uses the transputer, what they added to it to build a fast vector machine. Attention given to running a ray tracer. [Deering 88] Michael Deering (Sun Microsystems), Stephanie Winner (Apple Computer), Bic Schediwy (Hewlett Packard Labs), Chris Duffy (Schlumberger Palo Alto Research) & Neil Hunt (Schlumberger Palo Alto Research), "The Triangle Processor and Normal Vector Shader: A VLSI System for High Performance Graphics", Computer Graphics,, vol. 22, no. 4, (Proc. SIGGRAPH '88), August 1988, pp. 21-30. Since all polygons can be converted to triangles, they present a system that will draw only triangles, but draw them very fast. Uses a deep pipeline. Provides full Phong shading, and anti-aliasing by oversampling. Also supports texture mapping. [Denault 87] Damian Denault, Eric Ryherd, John Torborg, Robert Tosi & Ross Werner (Raster Technologies, Inc), "VLSI Drawing Processor Utilizing Multiple Parallel Scan-Line Processors," Advances in Computer Graphics Hardware II, Record of Second Eurographics Workshop on Graphics Hardware, 1987, pp. 167-182. The GX4000 system, which uses pipelining and parallelism to draw 4 scan-lines at a time. The system is both general and fast. The basic operations are described, as well as the architecture. Each display processor is made up of 5 VLSI processors: 1 master and 4 slaves, where the slaves handle Red, Green, Blue, and Depth values. [DeRose 87] Tony D. DeRose, Lawrence Snyder & Chyan Yang (University of Washington), "Near-Optimal Speedup of Graphics Algorithms Using Multigauge Parallel Computers," Proceedings of the 1987 International Conference on Parallel Processing, University Park, Pennsylvania, The Pennsylvania State University Press, 1987, pp. 289-294. They describe the uses of multigauging. For example, when only 10 bits per integer are needed, they stuff 3 into a 32 bit big integer, signal the system to enter multigauge mode, and voila! - three times the speed. Just requires a switch and three processors in parallel (for this example). [Devai 87] F. Devai (Hungarian Academy of Sciences, Budapest), "An O(log N) Parallel Time Exact Hidden-Line Algorithm," Advances in Computer Graphics Hardware II, Record of Second Eurographics Workshop on Graphics Hardware, 1987, pp. 47-63. An algorithm which is nicely adaptable to parallel systems is presented, which allows a speedup of factor P by using P processors. Both practical and theoretical models are presented. Also includes a good review of algorithmic work being done. While this is a hidden line algorithm, it is suggested that extension to hidden surface is possible. [Dew 85] Peter Dew, John Dodsworth & David Morris (The University, Leeds, England), "Systolic Array Architectures for High Performance CAD/CAM Workstations," Fundamental Algorithms for Computer Graphics, NATO ASI Series, vol. F17, Springer-Verlag, 1985, pp. 659-694. The use of systolic array computers for graphics. This type of computer is useful because "1) it is a simple and regular design, 2) it exploits parallelism by pipelining, and 3) the processing elements communicate only with their neighbors in a synchronous fashion. These advantages mean that systolic systems are particularly well suited for VLSI implementation." (page 664). They give a general description of systolic systems, draw comparisons with the transputer, the CMU warp cell, and the NCR GAPP chip. They show how CSG algorithms could be implemented on a systolic system. [Deyo 88] Rod Deyo, John A. Briggs & Pete Doenges (Evans & Sutherland), "Getting Graphics in Gear: Graphics and Dynamics in Driving Simulation," Computer Graphics, vol. 22, no. 4, (Proc. SIGGRAPH '88), August 1988, pp. 317-326. They describe a system for modeling vehicles in a naturally parallel manner. The system can be used to animate (in real time) the movement of a vehicle over any terrain. For example, they describe the modeling of a front suspension system. Interesting reading! [Dippe 84] Mark Dippe & John Swensen (University of California, Berkeley), "An Adaptive Subdivision Algorithm and Parallel Architecture for Realistic Image Synthesis," Computer Graphics, vol. 18, no. 3, (Proc. SIGGRAPH '84), July 1984, pp. 149-158. An algorithm and architecture that allows dynamic load balancing for ray tracing. Using a 3D array of processors, they divide space into blocks and assign processors to these blocks. They use message passing between processors to move boundaries when a processor is overloaded. An interesting feature is that when the system is overloaded, rays get dropped, so image quality is reduced. The system has some fault tolerance built in. [Drebin 88] Robert A. Drebin, Loren Carpenter & Pat Hanrahan (PIXAR), "Volume Rendering," Computer Graphics, vol. 22, no. 4, (Proc. SIGGRAPH '88), August 1988. An image display system for rendering volumetric data. Their system handles color and opacity better than most other systems, and produces some stunning images. [Dyer 87] Scott Dyer & Scott Whitman (Ohio Supercomputer Project, Ohio State University), "A Vectorized Scan-Line Z-Buffer Rendering Algorithm," IEEE Computer Graphics & Applications, July 1987, pages 34-45. Finally, a study of vectorizing a general hidden surface algorithm. Compare with Plunkett and Bailey's work. They rely very heavily on a vectorizing compiler. They draw comparisons between their algorithm, which has been reworked to run better under a vector machine, compiled using vector and nonvector optimizations. The algorithm and data structures are discussed in detail. Anti-aliasing is discussed. [Eyles 87] John Eyles, John Austin, Henry Fuchs, Trey Greer & John Poulton (University of North Carolina, Chapel Hill), "Pixel-Planes 4: A Summary," Advances in Computer Graphics Hardware II, Record of Second Eurographics Workshop on Graphics Hardware, 1987, pp. 183-207. A final report on the Pixel-Planes system. See also [Fuchs 85]. [Felger 88] W. Felger, M. Gobel, R. Ziegler & P. Zuppa (Fraunhofer Gesellschaft AGD, FRG), "The Realization of a Multiprocessor GKS Workstation," Parallel Processing for Computer Vision and Display, International Conference, University of Leeds, UK, 12-15 January, 1988. Describes a parallel approach to supporting the GKS standard. System is divided into a GKS module, WISS modules, OUTPUT modules, INPUT modules, and software and hardware modules. Discusses the functional distribution, object distribution, and multiprocessor GKS master slave relationships. Built on machine called HoMuk (homogeneous multiprocessor kernel). [Finch 87] H. R. Finch, M. Agate, A. A. Garel, P. F. Lister & R. L. Grimsdale (University of Sussex), "A Multiple Application Graphics Integrated Circuit - MAGIC II," Advances in Computer Graphics Hardware II, Record of Second Eurographics Workshop on Graphics Hardware, 1987, pp. 81-92. A new version of the MAGIC chip. The MAGIC II chip can perform all necessary graphic operations required in a complete system. Various architectures are outlined, for both the low and high end graphics market. The MAGIC chips are a product of the PRISM (Processors for Real Time Image Synthesis and Manipulation) project. The MAGIC chip is a VLIW system, and allows easy reconfiguration. See also [Agate 86], [Grimsdale 88]. [Fisher 87] Allan L. Fisher, Peter T. Highnam &Todd E. Rockoff (Carnegie Mellon University), "Architecture of a VLSI SIMD Processing Element," VLSI in Computers and Processors, Computer Society Press, Rye Brook, New York 1987. The SLAP (Scan Line Array Processor) and how it can be used in a three-stage pipeline. Used mainly for vision systems. [Fiume 83] Eugene Fiume, Alain Fournier (University of Toronto) & Larry Rudolph (Carnegie-Mellon), "A Parallel Scan Conversion Algorithm with Anti-Aliasing for a General-Purpose Ultracomputer," Computer Graphics, vol. 17, no. 3, (Proc. SIGGRAPH '83), July 1983, pp. 141-150. A scan conversion algorithm is made to run well on the Ultracomputer. Special attention paid to anti-aliasing. They add one simple instruction to the Ultracomputer instruction set (RepMin), but other than that it's a nice fit. [Fuchs 77] Henry Fuchs (University of Texas at Dallas), "Distributing a Visible Surface Algorithm over Multiple Processors," Proceedings of the 1977 ACM Annual Conference, Seattle, WA, October 1977, pp. 449-451. A design for a parallel implementation of the z-buffer algorith, including a discussion of coherence issues. [Fuchs 85] H. Fuchs, J. Goldfeather, et. at. (University of North Carolina at Chapel Hill), "Fast Spheres, Shadows, Textures, Transparencies, and Image Enhancements in Pixel-Planes," Computer Graphics, vol. 19, no. 3, (Proc. SIGGRAPH '85), July 1985, pp. 111-120. Fuchs' Pixel-Planes machine is explained in general. See [Eyles 87] for a final report. Explanation of how the machine can process linear equations, and gives several algorithms for display. Also published in Advances in Computer Graphics I, EUROGRAPHIC 86. [Fuchs 89] Henry Fuchs, et. al, "Pixel-Planes 5: A Heterogeneous Multiprocessor Graphics System Using Processor-Enhanced Memories," Computer Graphics, vol. 23, no. 3, (Proc. of SIGGRAPH '89), July 1989. The new Pixel-Planes machine is outlined and it's limitations and power discussed. The system is more flexible than earlier Pixel-Planes machines, built around a ring network, and supports a variable number of Graphic Processors and Renderers. Report on how they support PHIGS. [Fujimoto 86] A. Fujimoto, T. Tanaka, K. Iwata, "ARTS: Accelerated Ray Tracing System," IEEE Computer Graphics and Applications, vol. 6, no. 4, pp. 16-26. Describes an encoding format, similar to octrees, which allows ray tracing to become as fast as other rendering methods for large databases. Good review of other techniques used to speed up ray tracing. Their method, SEADS (Spatially Enumerated Auxiliary Data Structures), "provides an environment for ray tracing that outpaces the hybrid octree approaches ... by an order of magnitude. Various experimental results have shown that the rendering time is virtually independent of the number of objects in the scene. When the number of objects is very large, ray tracing - despite its reputation for ineffiency - actually becomes faster than other rendering methods." [Gaudent 88] Severin Gaudent, Richard Hobson, Pradeep Chilka & Thomas Calvert (Simon Fraser University), "Multiprocessor Experiments for High Speed Ray Tracing," ACM Transactions on Graphics, vol. 7, no. 3, July 1988. Good review of previous work. They classify space into shells (bounding volumes), starting from the parent shell (the scene) to the leaf nodes (primitives). They divide processing into three major tasks which are easy to schedule and pipeline, and then define a processor called a PERT (Pipelined Engine for Ray Tracing) which can support these tasks and work either separately or in parallel. A powerful, flexible system. [Gharachorloo 88] Nadar Gharachorloo, Satish Gupta, et. al., "Subnanosecond Pixel Rendering," Computer Graphics, vol. 22, no. 4, (Proc. SIGGRAPH '88), August 1988, pp. 41-49. An example of work done to speed up displays at the scan-line level. Uses a systolic array of pixel processors. Each SAGE (Systolic Array Graphics Engine) processor handles 256 pixels at a time. Reviewed in [Fuchs 89]. [Gharachorloo 89] Nader Gharachorloo, Satish Gupta (IBM T. J. Watson Research), Robert F. Sproull & Ivan E. Sutherland (Sutherland, Sproull & Asso.), "A Characterization of Ten Rasterization Techniques," Computer Graphics, vol. 23, no. 3, (Proc. of SIGGRAPH '89), July 1989, pp. 355-368. A review of rasterization techniques (including those using parallel processing) showing their strengths and deficiencies, and suggestions for new architectures for future raster graphics systems. [Ghosal 86] Dipak Ghosal & L. M. Patnaik (Indian Institute of Science), "Parallel Polygon Scan Conversion Algorithms: Performance Evaluation On A Shared Bus Architecture," Computers & Graphics, vol. 10, no. 1, Pergamon Press Ltd, 1986, pp. 7-25. Outlines 3 parallel scan conversion systems and discusses how they perform on a shared bus machine. Good description of data structures used and the general algorithm, and how it can be parallelized. [Glassner 84] Andrew S. Glassner (University of North Carolina, Chapel Hill), "Space Subdivision For Fast Ray Tracing," IEEE Computer Graphics & Applications, October 1984, pages 15-22. "If we want to reduce the time spent on ray-object intersections, we have at least two choices. We can speed up the intersection process itself, possibly with specialized hardware. Alternately, we can reduce the number of ray-object intersections that must be made to fully trace a given ray." Goes onto to describe how to use octrees to reduce the number of intersection tests. [Glassner 85] Andrew Glassner & Henry Fuchs (University of North Carolina, Chapel Hill), "Hardware Enhancements For Raster Graphics," Fundamental Algorithms for Computer Graphics, vol. F17, Springer-Verlag, NATO ASI Series, 1985, pp. 631-658. A good overview of what has happened in the field of raster graphics to make it go fast. They discuss how VLSI and parallelism have been exploited. This is a good survey paper, covering all areas of raster graphics, the various approaches taken to speed things up, and what tomorrow's display should be able to do. Lots of references. [Goldfeather 86] Jack Goldfeather (Carleton College), Jeff Hultquist & Henry Fuchs (University of North Carolina, Chapel Hill), "Fast Constructive Solid Geometry Display in the Pixel-Powers Graphics System," Computer Graphics, vol. 20, no. 4, (Proc. SIGGRAPH '86), August 1986, pp. 107-116. A new Pixel- machine that can display fully evaluated CSG objects. Examples given. [Goldwasser 88] S.M. Goldwasser et al (Dynamic Digital Displays, USA), "High-Performance Graphics Processors for Medical Imaging Applications," Parallel Processing for Computer Vision and Display, International Conference, University of Leeds, UK, 12-15 January, 1988. How to display the data generated by physicians using CT, MR, and PET machines. See also Kaufman's work. They store data in voxel format. The architecture of their system is outlined. [Goral 84] Cindy M. Goral, Kenneth E Torrance, Donald P. Greenberg & Bennett Battaile (Cornell University), "Modeling the Interaction of Light Between Diffuse Surfaces," Computer Graphics, vol. 18, no. 3 (Proc. SIGGRAPH '84), July 1984, pp. 213-222. The classic reference on radiosity. [Green 88] S. A. Green, D. J. Paddon & E. Lewis (University of Bristol, UK), "A Parallel Algorithm and Tree-based Computer Architecture for Ray Traced Computer Graphics," Parallel Processing for Computer Vision and Display, International Conference, University of Leeds, UK, 12-15 January, 1988. Good article describing how to support ray tracing for large databases and still have adequate speed. They use an octree type space subdivision, a pyramid type processor arrangement for task management, and a LRU (Least Recently Used) object holding pattern to hold onto objects needed to be tested for intersection. [Green 89] S. A. Green & D. J. Paddon (University of Bristol, England), "Exploiting Coherence for Multiprocessor Ray Tracing," IEEE Computer Graphics and Applications, November 1989. When using ray tracing in a limited memory distributed processing system, both data coherence and caching techniques can be used to allow large image databases to be displayed when ray tracing. They discuss sampling techniques to load balance the system. Data coherence is a new form of coherence; they find it very exploitable. [Greenshields 88] I. R. Greenshields (University of Connecticut), "A Dynamically Reconfigurable Multimodal Architecture for Image Processing," Parallel Processing for Computer Vision and Display, International Conference, University of Leeds, UK, 12-15 January, 1988. Different flavors of machines are presented and discussed, and a mixture of SIMD and MIMD techniques is used in the final system. [Grimes 89] Jack Grimes (MASS Microsystems), Les Kohn & Rajeev Bharadhwaj (Intel), "The Intel i860 64-bit Processor: A General Purpose CPU with 3D Graphics Capabilities," IEEE Computer Graphics and Applications, July 1989. This chip and others like it are changing the shape of the computer industry. General purpose CPU optimized for graphics, with multiple processing units on board. Yesterday's supercomputer on a chip. [Gupta 81] Satish Gupta, Robert Sproull (Carnegie-Mellon) & Ivan Sutherland (Sutherland, Sproull & Asso.), "A VLSI Architecture for Updating Raster Scan Displays," Computer Graphics, vol. 15, no. 3, (Proc. SIGGRAPH '81), August 1981, pp. 71-78. Smart memory chips that support high speed bitblit, anti-aliasing, etc. [Hagen 86] P.J.W. ten Hagen, A.A.M. Kujik & C.G. Trienekens (Centre for Mathematics and Computer Science, Amsterdam), "Display Architecture for VLSI-based Graphics Workstations," Advances in Computer Graphics Hardware I, Record of First Eurographics Workshop on Graphics Hardware, 1986, pp. 3-16. A complete 3D workstation is defined with full visualization (lighting, transparency, reflection, refraction) functionality. A pipelined system is outlined which contains specific modules. They go on to define some necessary operations, and different levels the workstation could operate in. See also [Kuijk 87], [Akman 87]. [Hiltebrand 88] E.G. Hiltebrand (ETH, Switzerland), "Hardware Architecture with Transputers for Fast Manipulation of Volume Data," Parallel Processing for Computer Vision and Display, International Conference, University of Leeds, UK, 12-15 January, 1988. Image 2D and 3D work, mostly hardware description. Tried a shaded surface remover. [Hu 85] Mei-Cheng Hu (IBM Federal Systems Division) & James D. Foley (George Washington University), "Parallel Processing Approaches To Hidden Surface Removal In Image Space," Computers & Graphics, vol. 9, no. 3, Pergamon Press Ltd, pp. 303-217. Good survey of hidden surface algorithms and parallelism. Outlines problems with load balancing, coherence vs. parallelism, and how processors are distributed (architectures). Also touches on fault tolerance. Lots of timing tests. [Hudson 88] N. A. Hudson (Stonefield Systems, UK), "The CLIP 3000 Parallel Image Processor," Parallel Processing for Computer Vision and Display, International Conference, University of Leeds, UK, 12-15 January, 1988. The CLIP system, including a chip specifically built to support image processing. Lots of promoting. Uses the transputer. [Ishihata 87] Hiroaki Ishihata, Masanori Kakimoto, Kouichi Inoue, Mitsuo Ishi, Gensuke Goto & Yoshinori Hatano (Fujitsu Ltd), "VLSI for the Cellular Array Processor," VLSI in Computers and Processors, Rye Brook, New York, Computer Society Press, 1987. How to use the CAP (Cellular Array Processor) to build a general purpose processor farm which can be used for image generation, including ray tracing. They review basic interconnection topologies. [Jansen 86a] Frederick W. Jansen (Delft University of Technology), "A Pixel-Parallel Hidden Surface Algorithm For Constructive Solid Geometry," Proceedings of European Computer Graphics Conference and Exhibition, The Computer Interface, 1986, pp. 29-40. A VLSI solution to the CSG display problem. The work appears to be similar to the Pixel-Powers system. They show ways of reducing the number of intersection tests which must be performed. The support for CSG boolean operations relies upon a system similar to the Z-buffer test. [Jansen 86b] Frederik W. Jansen (Delft University of Technology), "CSG Hidden Surface Algorithms for VLSI Hardware Systems," Advances in Computer Graphics Hardware I, Record of First Eurographics Workshop on Graphics Hardware, 1986, pp. 75-82. Review of basic ray tracing methods to evaluate and display CSG objects, similar to Pixel-Powers. They discuss operations necessary to display CSG objects, and outline a basic algorithm to accomplish the needed transformations. [Jevans 89] David A. J. Jevans (University of Calgary), "A Review of Multi-Computer Ray Tracing," Ray Tracing News, vol. 3, no. 1, (May 1989), Andrew S. Glassner, ed., pp. 8-15. "Major works in the field of parallel ray tracing are reviewed. A new technique for multi-computer ray tracing is outlined. Future trends are discussed." [Kaplan 79] Mark Kaplan & Don P. Greenberg, "Parallel Processing Techniques for Hidden Surface Removal," Computer Graphics , vol. 13, no. 2, (Proc. SIGGRAPH '79), 1979, pp. 300-307. Implementation of parallel versions of Warnock's and Weiler's algorithms. Fairly brief, but interesting. [Kaufman 86] Arie Kaufman (State University of New York at Stony Brook), "Memory Organization for a Cubic Frame Buffer," The Computer Interface, Proceedings of European Computer Graphics Conference and Exhibition, 1986, pp. 93-100. A voxel-based frame buffer. Voxel-based systems are good for displaying volume data, as might be found in medical imaging (CT scans), for example. The organization of the system allows fast viewing of the data, but it seems to require enormous amounts of memory to hold the voxels (n3 voxels, where a voxel is usually 8 bits). [Kaufman 88a] Arie Kaufman (State University of New York at Stony Brook), "The CUBE Workstation - a 3D Voxel-Based Graphics Environment," The Visual Computer, vol. 4, Springer-Verlag, 1988, pp. 210-221. An entire workstation is outlined, based on a voxel breakdown of the image. The workstation's architecture is outlined. [Kaufman 88b] A. Kaufman & R. Bakalash (SUNY at Stony Brook), "Parallel Processing for 3D Voxel-Based Graphics," Parallel Processing for Computer Vision and Display, International Conference, University of Leeds, UK, 12-15 January, 1988. Discussion of how parallel processing is used to support the CUBE workstation. [Kedem 88] G. Kedem (Duke University), "The Ray-Casting Machine," Parallel Processing for Computer Vision and Display, International Conference, University of Leeds, UK, 12-15 January, 1988. A pipelined bit serial machine that directly supports CSG display. Discussion of CSG, and of the basic architecture. The CSG trees need to be restructured, and then the objects can be correctly classified. There is much discussion of the architecture. [Kilgour 85] Alistair C. Kilgour (University of Glasgow), "Parallel Architectures For High Performance Graphics Systems," Fundamental Algorithms for Computer Graphics, NATO ASI Series, vol. F17, Springer-Verlag, 1985, pp. 695-703. They propose a new classification scheme for parallel display architectures: "polygon serial" (one processor per pixel), and "pixel serial" (one processor per graphic object). They then go on to classify various proposed architectures. [Kobayashi 87] Hiroaki Kobayashi, Tadao Nakamura &Yoshihara Shigei (Tohuku University), "Parallel Processing of an Object Space For Image Synthesis Using Ray Tracing," The Visual Computer, no. 3, Springer-Verlag, 1987, pp. 13-22. Using a pre-built octree, they speed up ray tracing. They describe the architecture of their system and how tasks can be distributed to the different processors using an adaptive subdivision graph. A static load balancing approach. [Kobayashi 88] Hiroaki Kobayashi (Tohuku University), Satoshi Nishimura (University of Tokyo), Hideyuki Kubota (Yamato Research Laboratory), Tadao Nakamura (Tohuku University) & Yoshihara Shigei (Toyo University), "Load Balancing Strategies For A Parallel Ray-Tracing System Based On Constant Subdivision," The Visual Computer, vol. 4, Springer-Verlag, 1988, pp.197-209. A static load balancing scheme for ray tracing and an architecture to support the algorithm. Discusses how to map the objects to the processors. Then they present a hierarchical system that has both static and dynamic load balancing capabilities. [Kochevar 89] Peter D. Kochevar (Cornell University), Computer Graphics on Massively Parallel Machines, Ph.D. thesis, Cornell University, August, 1989. A parallel system which models light as waves, and an implementation of this system on the Connection Machine. Waves - cowabunga! [Kuijk 87] A. A. M. Kuijk, P. J. W. ten Hagen & V. Akman (Centre for Mathematics and Computer Science, The Netherlands), "An Exact Incremental Hidden Surface Removal Algorithm," Advances in Computer Graphics Hardware II, Record of Second Eurographics Workshop on Graphics Hardware, 1987, pp. 21-37. An algorithm and system which allows incremental editing of surface definitions within a new architecture. The system is more efficient than other systems. See also [Akman 87], [Hagen 86] for other work by this group. [Kunii 88] T. L. Kunii (University of Tokyo), "The Design of a Parallel Processing System for Computer Graphics," Parallel Processing for Computer Vision and Display, International Conference, University of Leeds, UK, 12-15 January, 1988. Using ray tracing as an example problem, discusses a new static task assignment algorithm and how it can be run on a new system to support ray tracing. Good discussion of task assignment algorithm. [Lasseter 87] John Lasseter (PIXAR), "Principles of Traditional Animation Applied to 3D Computer Animation," Computer Graphics, vol. 21, no. 4, (Proc. SIGGRAPH '87), August 1987. The basics of animation and how it can all be done on a computer. Beautiful illustrations of Luxo Jr. and Sr. hopping around, and Andre scratching his belly. Unfortunately, not really about parallelism. [Levinthal 84] Adam Levinthal & Thomas Porter (Lucasfilm Ltd), "Chap - A SIMD Graphics Processor," Computer Graphics, vol. 18, no. 3, (Proc. SIGGRAPH '84), July 1984., pp. 77-82. Special purpose SIMD system which operates on Red, Green, Blue, and Alpha in parallel. They call it "digital pixel processing." [Musgrave 88] F. Kenton Musgrave, "Grid Tracing: Fast Ray Tracing for Height Fields," Yale University Dept. of Computer Science Research Report no. 639. An implementation of ray tracing using Linda. [Mitsuya 87] Eiji Mitsuya, Yoshiaki Tamamura & Takaaki Akimoto (NTT Electrical Communications Laboratories), "A Multiprocessor System For Three-Dimensional Graphics," Proceedings of 1987 IEEE International Conference on Computer Design: VLSI in Computers and Processors, Rye Brook, New York Computer Society Press, 1987, pp. 316-327. More uses of the MAGIC chip. They describe a complete graphics system. [Moravec 81] Hans P. Moravec (Carnegie-Mellon), "3D Graphics and the Wave Theory," Computer Graphics, vol. 15, no. 3, (Proc. SIGGRAPH '81), July 1981, pp. 289-296. A general overview of a new way of viewing light for computer graphics. He suggests using waves as the basis, and discusses the computational requirements and new capabilities. [Nemoto 86] K. Nemoto & T. Omachi, "An Adaptive Subdivision by Sliding Boundary Surfaces for Fast Ray Tracing," Proceedings of the Conference on Graphics Interface, 1986, pp. 43-48. They describe a dynamic load-balanced ray tracer. One of the first load-balanced ray tracers. [NeXT 89] NeXT Product Literature, 1989 [Nickolls 88] P.M. Nickolls & T.W. Cole (University of Sydney, Australia), "A Fault Tolerant Processor Array for Image Analysis," Parallel Processing for Computer Vision and Display, International Conference, University of Leeds, UK, 12-15 January, 1988. A fault tolerant image system, similar to the CLIP and MESH systems. SIMD machine. [Niimi 84] Haruo Niimi (Kyoto University), Yoshirou Imai (Takuma Radio Technical College), Masayoshi Murakami (Nippon Denshi Kagaku Co., Ltd), Shinji Tomita & Hiroshi Hagiwara (Kyoto University), "A Parallel Processor For Three-Dimensional Color Graphics," Computer Graphics, vol. 18, no. 3, (Proc. SIGGRAPH '84), July 1984, pp. 67-76. An algorithm and architecture to allow fast hidden surface display called EXPERT (EXpandable Parallel Processor Enhancing Real Time Scan Conversion). Using a scan line algorithm, it splits the image space for each processor, and does well in conserving coherence. EXPERT contains several SLP (Scan-Line Processors), which contain several slave PXP (Pixel Processors). They keep a active segment list updated to speed things up. [Nishimura 83] Hitoshi Nishimura, Hiroshi Ohno, Toru Kawata, Isao Shirakawa & Koichi Omura (Osaka University), "LINKS-1: A Parallel Pipelined Multimicrocomputer System For Image Creation," Proc. of the 10th Symposium on Computer Architecture, (SIGARCH), June 1983, pp. 387-394. A parallel machine for graphics that has a pipelined architecture, allowing a general approach to different graphics problems. [Ollis 88] John Ollis & Peter Borgwardt (Tektronix, Inc.), "The Parallel Processing Picture Buffer," Occam User Group Meeting, April 11, 1988. Transputers are used with a reconfigurable distributed frame buffer. "In the prototype we have built, the quilting pattern has been made programmable to allow the pattern to be optimized for the algorithm being run." [Owczarczyk 88] J. Owczarczyk (University of St. Andrews, UK), "Ray Tracing: A Challenge for Parallel Processing," Parallel Processing for Computer Vision and Display, International Conference, University of Leeds, UK, 12-15 January, 1988. A survey of work done to speed up ray tracing, including parallel attempts. This is a good survey that covers the major areas, including a good review of Plunkett and Bailey's work. [Page 88] I. Page (University of Oxford, UK), "The Disputer : A Dual Paradigm Parallel Processor for Graphics and VIsion," Parallel Processing for Computer Vision and Display, International Conference, University of Leeds, UK, 12-15 January, 1988. A 256 SIMD and 42 MIMD parallel machine useful for image processing and graphics. Good discussion of how the system is designed. Subparts of the system include the RasterOp (or BitBLT), and the DisArray. [Parke 80] Frederic I. Parke, "Simulation and Expected Performance Analysis of Multiple Processor Z-Buffer System," Computer Graphics,, vol 14, no. 3, (Proc. SIGGRAPH '80), August 1980, pp. 48-56. Describes various proposed architectures and how well different hidden surface programs run on these machines (or are expected to). [Patterson 90] Jean E. Patterson, Paulett C. Liewer, Ruel H. Calalo (NASA Jet Propulsion Lab) & Farzin Manshadi (TRW), "Electromagnetic Scattering Analysis on a Hypercube Parallel Architecture," NASA Tech Brief, vol. 14, no. 1, item 59, January 1990. Demonstrates the applicability of a 128 node hypercube of 68020 processors for the solution of large electromagnetic scattering problems. After all, what is light other than electromagnetic radiation? [Pineda 88] Juan Pineda (Apollo Computer Inc), "A Parallel Algorithm for Polygon Rasterization," Computer Graphics, vol. 22, no. 4, (Proc. SIGGRAPH '88), August 1988, pp. 17-20. A parallel algorithm for rasterizing polygons is presented which also handles anti-aliasing. [PIXAR 89] PIXAR Product Literature, 1989. The PIXAR II, a graphics processor based on a network of transputers. [Plunkett 85] David J. Plunkett & Michael J. Bailey (Purdue University), "The Vectorization of a Ray-Tracing Algorithm for Improved Execution Speed," IEEE Computer Graphics & Applications, August 1985, pages 52-60. Great work, done apparently without the benefit of a vectorizing compiler (compare with Whitman's paper), using a CDC Cyber 205. Basic strategy is to fill up a queue with rays waiting to be processed, then do the intersection tests in vector mode. [Potmesil 89] Michael Potmesil & Eric M. Hoffert (AT&T Bell Laboratories), "The Pixel Machine: A Parallel Image Computer," Computer Graphics, vol. 23, no. 3, (Proc. of SIGGRAPH '89), July 1989, pp. 69-78. A discussion on the architecture of the Pixel Machine, a parallel system of DSP chips with a distributed frame buffer, and how it is used to display pictures. Compare with Pixel-Planes, the Connection Machine, and systolic array systems. One of the few machines of its type sold commercially. [Price 89] Martin Price & Greg Truman (Thorn EMI), "Radiosity in Parallel," Applications of Transputers, IOS Press, Washington, 1990 (Proceedings of the First International Conference on Applications of Transputers, August 1989), pp. 40-47. Parallel implementation of radiosity on a network of transputers. Performance increases linearly with the number of processors. [Priol 89] Thierry Priol & Kadi Bouatouch (Institut de Recherche en Informatique de Systemes Aleatoires, France), "Static Load Balancing For A Parallel Ray Tracing on a MIMD Hypercube," The Visual Computer, vol. 5, Springer-Verlag, 1989, pp. 109-119. Similar to Kobayashi's work. Algorithm implemented on a Intel IPSC/1. They review other work done to load balance ray tracers. They calculate the complexity of the scenes by sampling the image space, then allocating the same number of active (hit) rays per processor. See also the paper by Badouel, et. al. [Puech 90] Claude Puech, Francois Sillion & Christophe Vedel (Laboratoire d'Informatique de l'Ecole Normale Superieure, Paris, France), "Improving Interaction with Radiosity-based Lighting Simulation Programs," Computer Graphics, vol. 24, no. 2, March 1990 (Proceedings of the 1990 Symposium on Interactive 3D Graphics), pp. 51-57. Real-time display of radiosity images based on a two-pass method, which distributes the calculations across a network of processors. [Recker 90] Rodney J. Recker, David W. George & Donald P. Greenberg (Cornell University), "Acceleration Techniques for Progressive Refinement Radiosity," Computer Graphics, vol. 24, no. 2, March 1990 (Proceedings of the 1990 Symposium on Interactive 3D Graphics), pp. 59-66. Radiosity parallelized using a modified hemicube algorithm and discussions of the efficiency of the resulting system. [Rhodes 88] R.L. Rhodes & L. Serra (Univerisity of Bradford), "A Scan Conversion System for Real-Time Graphics," Parallel Processing for Computer Vision and Display, International Conference, University of Leeds, UK, 12-15 January, 1988. 3D display, including projection, clipping, and scan conversion. Only convex polygons. [Schneider 87] Bengt-Olaf Schneider (University of Tubingen, FRG), "Ray Tracing Rational B-Spline Patches in VLSI," Advances in Computer Graphics Hardware II, Record of Second Eurographics Workshop on Graphics Hardware, 1987, pp. 47-63. Because ray-surface intersections are so much more expensive in B-spline based systems, methods are proposed to reduce the cost of the intersections by implementing the intersection code in VLSI. The architecture of the VLSI system is outlined. [Short 86] Graham Short, Tom Preston & Mike Asal (Texas Instruments), "An Introduction To The Graphics System Processor," The Computer Interface, Proceedings of European Computer Graphics Conference and Exhibition, 1986, pp. 293-304. A general purpose graphics chip for both text and graphics. It is designed for fast bitblitting. They describe its general architecture and how it can be integrated into a system. [Sillion 89] Francois Sillion, "Lighting Simulation for Image Synthesis: Realism and Interactivity," Ph.D. thesis, University of Paris, 1989. Discusses a new formulation for combining diffuse and specular effects and presents a distributed algorithm for their computation. [Strasser 86] W. Strasser, "VLSI-Oriented Graphics System Design," Part 5, EUROGRAPHICS 1986, Springer-Verlag, pp. 153-186. An overview of how VLSI has been used to support graphics. [SUN 89] SUN Product Literature, 1989 Specifically, the TAAC-1 processor. [Sutherland 74] Ivan E. Sutherland, Robert F. Sproull & Robert A. Schumacker, "A Characterization of Ten Hidden-Surface Algorithms," Computing Surveys, vol. 6, No. 1, March 1974 A classic paper; describes all the major hidden surface algorithms of the time, and gives a classification scheme. [Sutherland 86] Robert J. Sutherland (University of Glasgow), "A Multiprocessor Architecture for High-Quality Interactive Displays," The Computer Interface, Proceedings of European Computer Graphics Conference and Exhibition, 1986, pp. 265-277. The system relies upon a deep framebuffer and a display list. Different connection schemes are discussed which allow fast panning of the screen image, both for 3x3 and 4x4 arrays. [Tampieri 89] Filippo Tampieri (Cornell Unversity), Global Illumination Algorithms for Parallel Computer Graphics, Masters Thesis, Program of Computer Graphics, Cornell University, Ithaca, NY, January 1989, pp. 7-12, 88-96. A review of methods to distribute lighting models across multiprocessors. Includes a discussion of possible parallel implementations of radiosity algorithms. [Tanimoto 83] Steven L. Tanimoto (University of Washington), "A Pyramidal Approach To Parallel Processing," Computer Graphics, vol. 17, no. 3, (Proc. SIGGRAPH '83), July 1983. A general purpose image display computer having a pyramid type architecture. The advantages of the machine appear to come from its mimicking the 'cone of vision' which is normally created by graphic display algorithms. [Tanner 88] P. P. Tanner, B. M. Fowler & K. S. Booth (University of Waterloo, Canada), "Experience with Graphics Support for a Multiprocessor Workstation," Parallel Processing for Computer Vision and Display, International Conference, University of Leeds, UK, 12-15 January, 1988. User interface work done with coprocessors, a tablet, and a frame buffer with bitbanks. [Thayer 89] Larry J. Thayer, "Custom VLSI in the 3D Graphics Pipeline," Hewlett-Packard Journal, December 1989, pp. 74-77. Describes the use of VLSI in the graphics pipeline of the HP 9000 TurboSRX. [Theoharis 88] T. Theoharis & I. Page (University of Oxford, UK), "Parallel Incremental Polygon Rendering on a SIMD Processor Array," Parallel Processing for Computer Vision and Display, International Conference, University of Leeds, UK, 12-15 January, 1988. Processor arrays, ala pixel machine, polygon filling, hidden surface, shading, both smooth and flat. The DAP (distributed array processor) is similar to their solution. [Torborg 87] John G. Torborg (Raster Technologies, Inc), "A Parallel Processor Architecture for Graphics Arithmetic Operations," Computer Graphics, vol. 21, no. 4, (Proc. SIGGRAPH '87), August 1987. A general purpose graphics processor which can be configured in parallel. They outline a complete graphics system and an implementation of PHIGS+. [Trotter 88] J. A. Trotter & W. R. Moore (University of Oxford, UK), "MESH: An Architecture for Image Processing," Parallel Processing for Computer Vision and Display, International Conference, University of Leeds, UK, 12-15 January, 1988. Another image processing system, like the CLIP system. Specifically designed for vision recognition, it is a fault tolerant system. [Ullner 83] M. K. Ullner (California Institute of Technology), Parallel Machines for Computer Graphics, Ph. D. Thesis, California Institute of Technology, Pasadena, 1983. Discusses how to parallelize ray tracing in various ways. One of the early studies of parallelizing ray tracing and how ray tracing might perform on different architectures. [Upson 88] C. Upson & S. Fangmeier (University of Illinois), "The Role of Visualisation and Parallelism in a Heterogeneous Supercomputing Environment," Parallel Processing for Computer Vision and Display, International Conference, University of Leeds, UK, 12-15 January, 1988. Discussion of the current problems faced in visualization of results generated by supercomputers, and why more work must be done to allow better display of the data sets generated. [Weinberg 81] Richard Weinberg (University of Minnesota, Cray Research), "Parallel Processing Image Synthesis and Anti-Aliasing," Computer Graphics, vol. 15, no. 3, (Proc. SIGGRAPH '81), August 1981. Presents a pipelined system for solving in "real-time" the aliasing problem. Also suggests processor per polygon mapping. [Whitman 88] Scott Whitman & Richard Parent (Ohio Supercomputer Project, Ohio State University), "A Survey of Parallel Hidden Surface Removal Algorithms," Proceedings of PIXIM '88, Paris, France, October 1988. A general survey of the different approaches taken to parallelize different hidden surface algorithms. "One must realize that as the number of processors in a system increases, the granularity of coherence is reduced." [Whitted 80] Turner Whitted (Bell Laboratories), "An Improved Illumination Model for Shaded Display," Communications of the ACM, vol. 23, no. 6, June 1980. The classic paper on ray tracing. Describes a global shading model and extensions to the original ray tracing model. He notes that up to 95% of the time is spent calculating ray-surface intersections and that there must be a way to speed things up. [Woodwark 84] J.R. Woodwark (University of Bath, UK), "A Multiprocessor Architecture For View Solid Models," Displays , Butterworth & Co., Publishers, Ltd, April 1984, pp. 97-103. Suggestions on how to distribute processors are given, with a survey of current ideas. Loading problems are discussed, and various test results are presented. [Yang 87] Chang-Gui Yang (Fujian Normal University, Fuzhou, China), "On Speeding Up Ray Tracing of B-Spline Surfaces," Computer-Aided Design, Butterworth & Co. (Publishers) Ltd, April 1987. How to speed up ray tracing of b-spline surfaces by using bounding boxes. In the same vein as Glassner's work. Review of other work, and comparisons. ----------------------end of bibliography--------------------------
aburke@ogicse.cse.ogi.edu (Andrew Burke) (08/01/90)
Since I'm still getting "could you please send me"'s, I'm worried that some folks haven't gotten the bibliography I posted after my initial posting. Sooo, if you get this message but you never got the bibliography (or you never get this...;-), send me mail and I'll send you your own personal copy of the bibliography. Please indicate that you never got the biblio - that way I know you just haven't caught up on your reading yet. andrew burke aburke@cse.ogi.edu "Reboot The System!"