jim@ektools.UUCP (James Hugh Moore) (09/21/87)
I have a question regarding the make utility. We have a VAX 11/750 running Ultrix (actually 2 11/750's - one runs Ultrix 2.0, the other is still at 1.2). One of our users is managing some source code for a project and is trying to use make and SCCS to keep track of things. Basically, he has asked me if there is a way of keeping source in one directory and objects in another and using one makefile. Having been over the make documentation and looked at the gnuemacs makefiles, it seems that you can change directories and run makes from makes, but not pick up paths from a common point. Basically we would like to specify paths from a common directory, and have different directories for source, objects, special testing software, etc. If someone can give us an explanation (and/or examples) of how to use relative paths in makefile, or Point us to further documentation (or products), or Suggest other alternatives, we would greatly appreciate it. Thank you very much. Please respond via email. May God Bless You, in Jesus Name Jim Moore - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - James H. Moore, Software Tools Group Product Software Engineering Lab Eastman Kodak Co. Email: allegra!rochester!kodak!ektools!jim USMail: Dept 47, EP 5-2, Eastman Kodak Co., Rochester, NY 14650 Disclaimer: Opinions expressed are my own, and DO NOT represent the opinions or policies etc of Eastman Kodak Co. as a whole. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
jdw@atexrd.UUCP (John Williams) (09/22/87)
We could also use any help in redirecting where the object modules go when
using make.
E-mail would be appreciated.
Thanks
--
John Williams
Editorial Pagination - Atex, Inc., A Kodak Company
{ll-xn,genrad,munsell}!atexrd!jdwsmdf@tut.cis.ohio-state.edu (Mark D. Freeman) (09/24/87)
In <831@ektools.UUCP> jim@ektools.UUCP (James Hugh Moore) writes: >Basically, he has asked me if >there is a way of keeping source in one directory and objects in another and >using one makefile. >we would like to specify paths from a common directory, and have different >directories for source, objects, special testing software, etc. I am in need of similar advice. I want: /foo = sources /foo/reg = objects /foo/special = objects created with certain #defines the regular ones don't have. putting in: *.obj: ..\*.c just doesn't hack it. Yes, I'm doing some things under MSDOS... Any ideas? -- Mark D. Freeman (614) 262-3703 StrongPoint Systems, Inc. mdf@tut.cis.ohio-state.edu 2440 Medary Avenue ...!cbosgd!osu-cis!tut.cis.ohio-state.edu!mdf Columbus, OH 43202 Guest account at The Ohio State University
snafu@ihlpm.ATT.COM (Wallis) (09/25/87)
In article <204@tut.cis.ohio-state.edu>, mdf@tut.cis.ohio-state.edu (Mark D. Freeman) writes: > In <831@ektools.UUCP> jim@ektools.UUCP (James Hugh Moore) writes: > >Basically, he has asked me if > >there is a way of keeping source in one directory and objects in another and > >using one makefile. > > >we would like to specify paths from a common directory, and have different > >directories for source, objects, special testing software, etc. > > I am in need of similar advice. I want: > > /foo = sources > /foo/reg = objects > /foo/special = objects created with certain #defines the regular ones > don't have. > > just doesn't hack it. Yes, I'm doing some things under MSDOS... On UNIX, the following should work. I'll base the example on the following directory structure (which I think is a little more common than the one above. proj |||| ------------------- || -------------- | -------||------ | | | | | bin include obj src Also, assume theat the makefile is in the 'src' directory. ---- # BASE == the root directory of the project BASE = .. SOURCE_DIR = $(BASE)/src INC_DIR = $(BASE)/include OBJ_DIR = $(BASE)/obj BIN_DIR = $(BASE)/bin PRODUCT = foobar CFLAGS = -c -I$(INC_DIR) LDFLAGS = -s SPEC_DEFS = -DJUNK=boffo OBJ_FILES = $(OBJ_DIR)/foo.o \ $(OBJ_DIR)/bar.o $(PRODUCT): $(OBJ_FILES) $(CC) $(LDFLAGS) -o $(PRODUCT) $(OBJ_FILES) $(OBJ_DIR)/foo.o: $(SRC_DIR)/foo.c $(INC_DIR)/hdr.h $(CC) $(CFLAGS) $(SRC_DIR)/bar.c $(OBJ_DIR)/bar.o: $(SRC_DIR)/bar.c $(INC_DIR)/hdr.h $(CC) $(CFLAGS) $(SPEC_DEFS) $(SRC_DIR)/bar.c ----- Whether or not these types of constructs work under MS-DOS depends on whose 'make' command you are using. I have one version of make that is almost totally compatible with unix make, and another that would not handle this at all. Note that the same techniques used above can be used with multiple source or object directories. If you need to be able to build multiple versions of a particular object with different #defines, try the following: $(OBJ_DIR_A)/foo.o: $(SRC_DIR)/foo.c $(INC_DIR)/hdr.h $(CC) $(CFLAGS) $(SPEC_DEFS_1) $(SRC_DIR)/bar.c $(OBJ_DIR_B)/foo.o: $(SRC_DIR)/foo.c $(INC_DIR)/hdr.h $(CC) $(CFLAGS) $(SPEC_DEFS_2) $(SRC_DIR)/bar.c $(PRODUCT_1): $(OBJ_FILES_1) $(CC) $(LDFLAGS) -o $(PRODUCT_1) $(OBJ_FILES_1) $(PRODUCT_2): $(OBJ_FILES_2) $(CC) $(LDFLAGS) -o $(PRODUCT_2) $(OBJ_FILES_2) Hope this helps. Let me kow if I confused you more than ever! Dave Wallis ihnp4!ihlpm!snafu AT&T Network Systems, Inc. (312) 510-6238
schaefer@ogcvax.UUCP (Barton E. Schaefer) (09/26/87)
In article <ihlpm.1413> snafu@ihlpm.ATT.COM (Wallis) writes: }In article <204@tut.cis.ohio-state.edu>, mdf@tut.cis.ohio-state.edu (Mark D. Freeman) writes: }>In <831@ektools.UUCP> jim@ektools.UUCP (James Hugh Moore) writes: }>>... a way of keeping source in one directory and objects in another and }>>using one makefile. }> }> I am in need of similar advice. }> }On UNIX, the following should work. I'll base the example on the following }directory structure ... }---- }SOURCE_DIR = $(BASE)/src }INC_DIR = $(BASE)/include }OBJ_DIR = $(BASE)/obj } [...] }$(OBJ_DIR)/foo.o: $(SRC_DIR)/foo.c $(INC_DIR)/hdr.h } $(CC) $(CFLAGS) $(SRC_DIR)/foo.c This works OK, but what if there are several dozen source files and corresponding objects? Do you really want to specify every single one of those dependencies and compilation commands, where the only thing that changes from line to line is the basename of the file? The VPATH variable (found in 4.3BSD make, among others) helps a little, but can't specify different object directories and leaves something to be desired even in terms of local objects depending on "remote" sources. For example, given the dependency foo : foo.o $(CC) $(CFLAGS) foo.o -o foo where foo.c is in a VPATH-specified directory, the "right " thing happens if you say "make foo". But if you type "make foo.o" (which works under the default ".c.o:" dependency if foo.c is in the same directory) simply does nothing -- doesn't even complain that it can't make foo.c. Is there any way to handle this? -- Bart Schaefer CSNET: schaefer@Oregon-Grad UUCP: ...{tektronix,verdix}!ogcvax!schaefer "This area is like heaven, and they want to turn it into California." -- Joseph Cook, Amish farmer, protesting highway construction
evas@euraiv1.UUCP (Eelco van Asperen) (09/29/87)
In article <1413@ihlpm.ATT.COM>, snafu@ihlpm.ATT.COM (Wallis) writes: > > $(OBJ_DIR)/foo.o: $(SRC_DIR)/foo.c $(INC_DIR)/hdr.h > $(CC) $(CFLAGS) $(SRC_DIR)/bar.c > > $(OBJ_DIR)/bar.o: $(SRC_DIR)/bar.c $(INC_DIR)/hdr.h > $(CC) $(CFLAGS) $(SPEC_DEFS) $(SRC_DIR)/bar.c This works but what I'ld really want are inference rules that "know" about sub-directories; fe. .c.o: cc $(CFLAGS) $< -o $(OBJ_DIR) $(OBJ_DIR)/foo.o: $(SRC_DIR)/foo.c $(INC_DIR)/hdr.h This apparently failes with the current make because a pathname ending in .o (fe. obj/foo.o) will not match the '.c.o' template that is defined for the inference rule so make will complain "don't know how to make foo.o". Unless someone can come up with a (valid) reason for this behaviour, I consider this a bug in make. Eelco van Asperen. -----------------------------------------+------------------------------ Erasmus University Rotterdam |uucp:mcvax!eurifb!euraiv1!evas Fac. of Economics, Computer Science Dept.|earn:asperen@hroeur5 PO.box 1738 / 3000 DR Rotterdam | T H E N E T H E R L A N D S |Yet Another Silly Signature. -----------------------------------------+------------------------------
beede@hubcap.UUCP (Mike Beede) (10/04/87)
On our Celerity system (a BSD derivative), make allows use
of the special name .PREFIXES, whose dependents specify
directories to search for sources when using the inference
rules.
The objects get created in the current directory, though.
There's probably some way around that . . .
--
Mike Beede
Computer Science Dept. UUCP: . . . !hubcap!beede
Clemson University INET: beede@hubcap.clemson.edu
Clemson SC 29634-1906 YOUR DIME: (803)656-{2845,3444}chris@nrcvax.UUCP (Chris Grevstad) (10/06/87)
schaefer@ogcvax.UUCP (Barton E. Schaefer) says: >... >The VPATH variable (found in 4.3BSD make, among others) helps a little, but >can't specify different object directories and leaves something to be desired >even in terms of local objects depending on "remote" sources. For example, >given the dependency > >foo : foo.o > $(CC) $(CFLAGS) foo.o -o foo > >where foo.c is in a VPATH-specified directory, the "right " thing happens if >you say "make foo". But if you type "make foo.o" (which works under the >default ".c.o:" dependency if foo.c is in the same directory) simply does >nothing -- doesn't even complain that it can't make foo.c. > >Is there any way to handle this? Uh, this worked ok for me. I am using the BSD4.3 make (with some local mods to handle the SYSV library stuff and the $(?:.o=.c) thing). It may be that what hacking I have done has changed the behavior of make, but I don't think so. ... Well, I just compiled up the vanilla make direct from downtown BSD4.3 and it still worked. Not sure what your problem is unless it's that you aren't using the 4.3 stuff. On a slightly different note, as long as I'm hacking on make (and have learned yacc), what kinds of things do you think make should be able to do? It must fit into the current vision of make, not the new make from Glen Fowler. -- Chris Grevstad cit-vax!elroy!nrcvax!chris@rutgers.edu hplabs!sdcrdcf!psivax!nrcvax!chris ihnp4!nrcvax!chris Where subtlety fails us we must simply make do with cream pies.