jml@ivory.SanDiego.NCR.COM (Michael Lodman) (12/03/88)
According to Motorola, the 88200 CMMU does not cache the page and
segment descriptors it fetches during a table walk. This would seem
to me to have a negative impact on performance. Is this standard
practise for table walks, and if not why did Motorola do it that way?
John Mashey, perhaps you could tell me if MIPS does this.
Michael Lodman (619) 485-3335
Advanced Development NCR Corporation E&M San Diego
mike.lodman@ivory.SanDiego.NCR.COM
{sdcsvax,cbatt,dcdwest,nosc.ARPA}!ncr-sd!ivory!jml
When you die, if you've been very, very good, you'll go to ... Montana.tom@nud.UUCP (Tom Armistead) (12/03/88)
In article <415@ncr-sd.SanDiego.NCR.COM> jml@ivory.SanDiego.NCR.COM (Michael Lodman) writes: >According to Motorola, the 88200 CMMU does not cache the page and >segment descriptors it fetches during a table walk. This would seem Wrong! The 88200 does cache page descriptors. Up to 56 page descriptors (each descriptor maps 4K of virtual space) can be cached in each CMMU. The page descriptor cache is managed by the CMMU. In addition, per CMMU, software can map up to eight 512K chunks of memory via the block address translation cache and avoid table walks on contiguous areas of memory (e.g. kernel text and data, i/o areas, etc.). --
mash@mips.COM (John Mashey) (12/03/88)
In article <415@ncr-sd.SanDiego.NCR.COM> jml@ivory.SanDiego.NCR.COM (Michael Lodman) writes: >According to Motorola, the 88200 CMMU does not cache the page and >segment descriptors it fetches during a table walk. This would seem >to me to have a negative impact on performance. Is this standard >practise for table walks, and if not why did Motorola do it that way? >John Mashey, perhaps you could tell me if MIPS does this. Yes. If it's in the cache, it's in the cache. -- -john mashey DISCLAIMER: <generic disclaimer, I speak for me only, etc> UUCP: {ames,decwrl,prls,pyramid}!mips!mash OR mash@mips.com DDD: 408-991-0253 or 408-720-1700, x253 USPS: MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086
tim@crackle.amd.com (Tim Olson) (12/03/88)
In article <1583@nud.UUCP> tom@nud.UUCP (Tom Armistead) writes: | In article <415@ncr-sd.SanDiego.NCR.COM> jml@ivory.SanDiego.NCR.COM (Michael Lodman) writes: | >According to Motorola, the 88200 CMMU does not cache the page and | >segment descriptors it fetches during a table walk. This would seem | | Wrong! The 88200 does cache page descriptors. Up to 56 page descriptors | (each descriptor maps 4K of virtual space) can be cached in each CMMU. The | page descriptor cache is managed by the CMMU. Yes, the translation is cached in the TLB entries, but I think the question was do the memory accesses that are performed during the table walk also get cached in the data cache? Or must they always go to main memory? -- Tim Olson Advanced Micro Devices (tim@crackle.amd.com)
paul@taniwha.UUCP (Paul Campbell) (12/05/88)
In article <1583@nud.UUCP> tom@nud.UUCP (Tom Armistead) writes: >In article <415@ncr-sd.SanDiego.NCR.COM> jml@ivory.SanDiego.NCR.COM (Michael Lodman) writes: >>According to Motorola, the 88200 CMMU does not cache the page and >>segment descriptors it fetches during a table walk. This would seem > > Wrong! The 88200 does cache page descriptors. Up to 56 page descriptors >(each descriptor maps 4K of virtual space) can be cached in each CMMU. The I think what he is really asking is 'does the 88200 cache the segment table entries used to read page table entries with?'. I've often thought about whether this is worth while or not, it probably is for 'medium' to 'large' size programs ('small' ones only need a few entries and fit in the TLB cache, 'large' to 'huge' ones may thrash). I think that simulation is probably the only way to find out and of course your mileage may vary for different architectures and different job mixes. Of course systems that do software TLB misses like the 29K and the MIPS chips take advantage of any data cache the system has since they treat both segment table entry accesses and page table entry accesses like any other access. (This helps you particularly for VERY large programs that are thrashing in the TLB cache because the data cache speeds up TLB refills) Paul -- Paul Campbell ..!{unisoft|mtxinu}!taniwha!paul (415)420-8179 Taniwha Systems Design, Oakland CA "Read my lips .... no GNU taxes"
jml@ivory.SanDiego.NCR.COM (Michael Lodman) (12/06/88)
In article <1583@nud.UUCP> tom@nud.UUCP (Tom Armistead) writes: >In article <415@ncr-sd.SanDiego.NCR.COM> jml@ivory.SanDiego.NCR.COM (Michael Lodman) writes: >>According to Motorola, the 88200 CMMU does not cache the page and >>segment descriptors it fetches during a table walk. > > Wrong! The 88200 does cache page descriptors. Mr. Armistead of Motorola, please re-read the question and try to answer it this time. I'm not asking you if the translated real addresses are maintained in the PATC, I'm asking if the data from the two fetches done during the table walk are placed in the d/i cache. If not, why not? Michael Lodman (619) 485-3335 Advanced Development NCR Corporation E&M San Diego mike.lodman@ivory.SanDiego.NCR.COM {sdcsvax,cbatt,dcdwest,nosc.ARPA}!ncr-sd!ivory!jml When you die, if you've been very, very good, you'll go to ... Montana.
tom@nud.UUCP (Tom Armistead) (12/10/88)
In article <432@ncr-sd.SanDiego.NCR.COM> jml@ivory.SanDiego.NCR.COM (Michael Lodman) writes: >In article <1583@nud.UUCP> tom@nud.UUCP (Tom Armistead) writes: >> Wrong! The 88200 does cache page descriptors. >Mr. Armistead of Motorola, please re-read the question and try to answer >it this time. I'm not asking you if the translated real addresses are >maintained in the PATC, I'm asking if the data from the two fetches done >during the table walk are placed in the d/i cache. If not, why not? If you want to post my emailed response, you may. --