jim@belltec.UUCP (Mr. Jim's Own Logon) (10/27/88)
In article <1988Oct25.180345.8888@utzoo.uucp>, henry@utzoo.uucp (Henry Spencer) writes: > In article <16901@shemp.CS.UCLA.EDU> casey@CS.UCLA.EDU (Casey Leedom) writes: > > It's been hinted at a couple of times that NeXT doesn't have any error > >detection on main memory. Is this true? If so, what was the rationale > >not to put it in? ... > > Probably because modern memory chips are much more reliable than the 4Kb > and 16Kb clunkers that caused the rush to error correction. > -- > The dream *IS* alive... | Henry Spencer at U of Toronto Zoology > but not at NASA. |uunet!attcan!utzoo!henry henry@zoo.toronto.edu While it is true that the small memory cell size and the reduced leakage make the later DRAMs less susceptable to alpha particla hits, this does not mean that the error checking is no longer required. The majority of memory errors are caused by noise (line noise, chip induced noise, peripheral induced noise, etc.). Each RAM chip is going to be variably sensitive to this noise, even from the same vendor their is a distribution of noise sensitivity. And when you compare from one chip lot to another, their is a wider distribution, and from one fab line to another, it gets even bigger. And in this day of RAM shortages, when you compare between one RAM vendor and another you will find that some RAMs will lose bits at regularly while others can withstand a nuclear blast. Anyway, with DOS who cares? Lose a bit and your program dies, no sweat. In UNIX, you lose an inode and there is hell to pay. You just can't afford to be uncertain about each byte off of memory. Multiple bit error checking is the best, parity is acceptable. No error checking is a bad design. Period. I still haven't heard a diffinitive answer: does the NeXT machiNe have any memory error checking? If it does not, this is (to me) the biggest mistake they could have made (yes, even bigger than no floppy and a 96 msec disk). -Jim Wall Bell Technologies Inc