josephc@nntp-server.caltech.edu (Simplelogic (Joseph)) (04/23/91)
Hello fellow netters. I am currently putting together a NEC V-53 computer project. Basically speaking, a high-performance Intel 80186-like processor with what I hope is zero-wait-state memory, all clocking at a nice and decent 16-MHz. According to the documentation that I have, the V-53 requires a 80ns access time to memory. That's not too bad of a problem if the CPU was attached directly to the DRAM's (will be using -70ns SIMM's); however, in order to implement direct-fly-by DMA (where the device puts the data on the data bus while the memory writes it in, or vice-versa), I need to buffer the output of the CPU, and the memory, and run them both through the system bus (with expansion, of course). My problem is that a couple of 74LS gates will already add up to about 40ns to the access time... Ergo, wait states - something that I don't want to have if I can get away without it. How have current 386 and 68040 (and other) based systems get around this timing bottle-neck? 74F/74ALS series chips? Unfortunately, there is a very limited availability, both in terms of what's being manufactured, and in terms of sourcing from distributors in small quanitities. I'd like some input as to how I can speed up overall access time while maintaining a fully-buffered architecture (crucial because it will be on a bus with lots of device on it). Thanks. -- Joseph (P.S., if anyone is curious, I am building a telephone exchange using National Semiconductor's SLIM units which basically will take care of 80% of the interfacing and analog <-> digital conversion on one 'chip'. The system is on a S-100 sized backplane, but with completely redefined lines, and [heavens!] -48V DC and two -48V "AC" lines...) -- Joseph I. Chiu, Department of Computer Science, Calif. Inst. of Technology 1-57 Fleming House, Caltech, Pasadena 91126. (818) 585-0393 josephc@coil.caltech.edu ...I don't know what I don't know
raoul@eplunix.UUCP (Nico Garcia) (04/24/91)
In article <1991Apr23.013116.3769@nntp-server.caltech.edu>, josephc@nntp-server.caltech.edu (Simplelogic (Joseph)) writes: > My problem is that a couple of 74LS gates will already add up to about 40ns > to the access time... Ergo, wait states - something that I don't want > to have if I can get away without it. Hmmm. I don't know how the clever digital people did it, but what's the net delay on a PAL down to these days? Also, can you cleverly run your gates off the previous clock cycle or the latter half of it? It's a bit of a kludge, but it might work.... -- Nico Garcia Designs by Geniuses for use by Idiots eplunix!cirl!raoul@eddie.mit.edu
lpdjb@brahms.amd.com (Jerry Bemis) (04/25/91)
In article <1067@eplunix.UUCP> raoul@eplunix.UUCP (Nico Garcia) writes: >In article <1991Apr23.013116.3769@nntp-server.caltech.edu>, josephc@nntp-server.caltech.edu (Simplelogic (Joseph)) writes: >> My problem is that a couple of 74LS gates will already add up to about 40ns >> to the access time... Ergo, wait states - something that I don't want >> to have if I can get away without it. > >Hmmm. I don't know how the clever digital people did it, but what's >the net delay on a PAL down to these days? Also, can you cleverly >run your gates off the previous clock cycle or the latter half of >it? It's a bit of a kludge, but it might work.... > > >-- > Nico Garcia 5nS PALs are out these days. Call AMD at 800 222-9323
henry@zoo.toronto.edu (Henry Spencer) (04/27/91)
In article <1991Apr23.013116.3769@nntp-server.caltech.edu>, josephc@nntp-server.caltech.edu (Simplelogic (Joseph)) writes: > My problem is that a couple of 74LS gates will already add up to about 40ns > to the access time... Ergo, wait states - something that I don't want... The original article of this hasn't wandered into zoo yet -- either we've got a propagation glitch or it had illegal headers and never made it -- but insofar as I understand the problem out of context, have you considered a faster TTL family like 74F? 74F is probably going to be less hassle than getting something like a PAL blown. -- And the bean-counter replied, | Henry Spencer @ U of Toronto Zoology "beans are more important". | henry@zoo.toronto.edu utzoo!henry
csg@pyramid.pyramid.com (Carl S. Gutekunst) (05/02/91)
>My problem is that a couple of 74LS gates will already add up to about 40ns >to the access time... Ergo, wait states - something that I don't want to >have if I can get away without it. Don't mess with F or ALS parts; the rise-times on those parts make for some difficult noise problems. Plain S will do. Intel and Signetics both make off- the-shelf birectional and unidirectional buffer chips that should do the job, with sub 10ns delays. Don't forget to keep your decoding and chip-select paths real short, too. In some cases you may find that pairs of tri-stated line buffers wire or'd will be faster than using equivalent birectional parts. (I think that's actually the way the Intel chips work.) I'm not aware of any PALs designed as line buffers; they are normally used for decoding or state machines. PALs require special equipment to blow their fuses anyway. (At least, you *want* the special equipment to avoid blowing the chip instead of the fuses.) <csg>