doon@unsvax.UUCP (Harry W. Reed) (04/19/87)
Hi, While looking at the 1986 Series 32000 databook, I've found reference to a 32310 FPC (Floating point controller). My question is "how does the 32310 differ from the proposed 32381 FPU ?". Cheers, Harry Reed, ...!unsvax!doon
roger@nsc.nsc.com (Roger Thompson) (04/20/87)
In article <145@unsvax.UUCP>, doon@unsvax.UUCP (Harry W. Reed) writes: > > While looking at the 1986 Series 32000 databook, I've found > reference to a 32310 FPC (Floating point controller). My question is > "how does the 32310 differ from the proposed 32381 FPU ?". > They differ in several ways ---- 1.) We had attempted to remove all references of the 310 from the data book, but alas ---- we missed in one or two places. Why remove it? Well, the implementation was one that would have interfaced the Weitek 1164/65 pair to the Series32000. Unfortunately, this solution turned out not to be as practical as first thought. The performance gained was not sufficient enough to justify the added expense(from a customers perspective) so that its price/performance ratio was not satisfactory. We decided to stop work on this effort. 2.) The 32381 is an active project due out of fab in the mid summer time frame. It is based on the 32081 but is done in CMOS and will operate at up to 30 MHZ. It is a single chip solution as opposed to being a multi-chip solution of the 310. The 381 supports the 081 instruction set plus a few other primitives. The device supports a 32 bit slave protocol. It has 64 bit internal registers and supports "early completion". The ALU has been enhanced to speed up adds and multiplies. Double precision floating multiplies can be done in 1 usec at 30 MHZ. Roger
mash@mips.UUCP (John Mashey) (04/21/87)
In article <4221@nsc.nsc.com> roger@nsc.nsc.com (Roger Thompson) writes: > 2.) The 32381 is an active project due out of fab in > the mid summer time frame. It is based on the 32081 > but is done in CMOS and will operate at up to 30 MHZ....... > up adds and multiplies. Double precision floating > multiplies can be done in 1 usec at 30 MHZ. Just out of curiosity, are there timings/cycle counts available for adds, divides? [This looks like 33 cycles for a DP multiply?] -- -john mashey DISCLAIMER: <generic disclaimer, I speak for me only, etc> UUCP: {decvax,ucbvax,ihnp4}!decwrl!mips!mash, DDD: 408-720-1700, x253 USPS: MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086
roger@nsc.nsc.com (Roger Thompson) (04/21/87)
In article <323@winchester.UUCP>, mash@mips.UUCP (John Mashey) writes: > > 2.) The 32381 is an active project due out of fab in > > the mid summer time frame. It is based on the 32081 > > but is done in CMOS and will operate at up to 30 MHZ....... > > up adds and multiplies. Double precision floating > > multiplies can be done in 1 usec at 30 MHZ. > Just out of curiosity, are there timings/cycle counts available for > adds, divides? [This looks like 33 cycles for a DP multiply?] Adds and subtracts are actually a little slower than multiplies. They are approx 1.4 usec. I don't have the exact numbers on divides with me, but recollection says its about 2 usec. Generally speaking, both single and double precision calculations take the same amount of time. ews up
mash@mips.UUCP (04/22/87)
In article <4222@nsc.nsc.com> roger@nsc.nsc.com (Roger Thompson) writes: > [re: NS32381 cycle counts] >Adds and subtracts are actually a little slower than multiplies. >They are approx 1.4 usec. I don't have the exact numbers >on divides with me, but recollection says its about 2 usec. >Generally speaking, both single and double precision calculations >take the same amount of time. To summarize, I think what's been said is that multiplies are about 30 cycles, adds about 50, and divides about 60, for DP. I'm not really familiar with 32081 timings: is the 32381 a bunch faster [in cycle counts], or is any speedup mainly from clock rate? I'm a lot more familiar with Whetstone/Linpack/etc ratings than actual FP cycle counts: are these numbers competitive? (at least with other microcoded parts like 80387 or 68881/68882?) -- -john mashey DISCLAIMER: <generic disclaimer, I speak for me only, etc> UUCP: {decvax,ucbvax,ihnp4}!decwrl!mips!mash, DDD: 408-720-1700, x253 USPS: MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086
roger@nsc.nsc.com (Roger Thompson) (04/23/87)
In article <326@winchester.UUCP>, mash@mips.UUCP (John Mashey) writes: > To summarize, I think what's been said is that multiplies are about > 30 cycles, adds about 50, and divides about 60, for DP. > I'm not really familiar with 32081 timings: is the 32381 a bunch > faster [in cycle counts], or is any speedup mainly from clock rate? > I'm a lot more familiar with Whetstone/Linpack/etc ratings than > actual FP cycle counts: are these numbers competitive? The internals of the 381 are about 40% faster than the older 081. Part of this is due to the slave protocol, part is due to enhancements in the ALU. Benchmark performance is unfortunately more contingent on the integer capabilities of the CPU at least as it relates to the Whetstone and the Linpack benchmarks. The 381 will operate with all series 32000 CPUs all the way from the 32008 to the 32532. At 10 MHZ with the 32016, you will get about 550 kwhets SP. The same part will get 2.8 to 3.0 Mwhets with the 532 at 30 MHZ. Roger