culberts@hpccc.HP.COM (Bruce Culbertson) (08/06/88)
I recently noticed a few features of the NS32000 architecture which I do not understand. Maybe someone could enlighten me. Why doesn't the SVC (supervisor call) instruction advance the program counter to the next instruction before pushing it onto the stack? Leaving the PC unchanged makes sense for some traps, where the user will usually want to retry the instruction causing the trap. With SVC however, the user wants to continue with the next instruction after the call has completed. As implemented, SVC is not a call in the usual sense. In contrast, the trace trap does do the expected thing; i.e. it advances the PC before pushing it onto the stack. Second, why don't the traps clear the interrupt enable flag? If the flag were cleared and the user wanted interrupts to remain on, he could easily turn them back on with only a few microseconds lost. With interrupts remaining on at the beginning of a trap, an important interlock is hard to achieve. The problem arises with multiple (nested) interrupts and traps. The outer (first) interrupt/trap should save the user state in a process table and restart a user process upon returning. Inner interrupts should merely save the running state and restore it upon returning. If interrupts were disabled on traps and interrupts, trap/interrupt handlers could increment a semaphore with which they could determine if they were inner or outer. With interrupts enabled, the semaphore cannot be implemented because another interrupt can sneak in before the semaphore is incremented. What solutions have operating system implementers found? Bruce Culbertson culberts@hplabs.hp.com
cjosta@taux01.UUCP (Jonathan Sweedler) (08/07/88)
In article <5980003@hpccc.HP.COM> Bruce Culbertson writes: >I recently noticed a few features of the NS32000 architecture which >I do not understand. Maybe someone could enlighten me. > >Second, why don't the traps clear the interrupt enable flag? Section 6.8.1 of the _Series 32000 Instruction Set Reference Manual_ describes the "Maskable/Non-Maskable Interrupt Sequence." Step 2 is: "Copy the Processor Status Register (PSR) into a temporary register, then clear PSR bits S, U, T, P and I." The I bit in the PSR is the Interrupt Enable bit. When the I bit is cleared, only Non-Maskable interrupts are accepted. Thus, after an interrupt is received, a 32000 series chip will ignore Maskable interrupts until told to do otherwise. And, of course, the RETT (Return from Trap) instruction restores the value of the PSR (not including the P bit) to its value before the interrupt. Thus, an interrupt scheme such as the one you proposed, is indeed possible in the 32000 series architecture. -- Jonathan Sweedler ====== National Semiconductor (Israel) UUCP: ...!{amdahl,hplabs,decwrl}!nsc!taux01!cjosta Domain: cjosta@taux01.nsc.com