starovic@cs.tcd.ie (Gradimir Starovic) (11/03/88)
We are using a locally developed work station based on the NS components. The problem that I am having seems to be related to the way I use the NS32202 ICU chip. A master ICU has only one slave ICU which is connected to IR1. The slave ICU is connected to a DMA 32203 controller. If DMA interrupt service routine executes a piece of code which tries to set bit 1 in the in service (ISRV) register it seems that we have an extra DMA interrupt. That code is called from other int service routines and it tries to ensure that it runs on the highest level of priority, but in the case when it's called from the DMA int routine it is not necessary as it already runs on that level. The data sheet mentions a 4-bit in-service counter which keeps track of the number of interrupts being serviced (for one slave ICU). Is it possible that if the CPU sets the bit in the ISRV which corresponds to a cascaded int when that int is already being serviced the in-service counter is incremented, so that the master ICU believes that one more int has happened? starovic@cs.tcd.ie The Distributed Systems Group, Comp. Science Department, Trinity College Dublin, Ireland