ward@cfa.harvard.EDU (Steve Ward) (12/11/88)
NS32016/NS32C016 CPU Board December 1, 1988
-------------------------- S. M. Ward
The CPU board is very simple, containing CPU, MMU, FPU, TCU, ICU, EPROM
memory, DRAM memory, and a PC I/O bus interface. The CPU board is physically
and electrically plug-compatible with PC/XT compatible computers as an 8-bit
PC I/O bus expansion board. A computer which supports the PC I/O bus, such
as a common PC/XT compatible computer, is used as an intelligent I/O server
for one or more CPU boards.
The main advantage of using the PC I/O bus is access to lots of existing
hardware at moderate prices. Further flexibility and savings are realized
when upgrading to a new CPU. To upgrade or expand to a new CPU, simply
plug in a replacement CPU board or an additional CPU board!
The common PC/XT and AT compatible computers will provide a low cost
host environment for the CPU board, providing peripherals and I/O
services. Better I/O performance can be attained by using a more
powerful PC bus computer as the host I/O server. A mother board with
8 PC I/O bus slots and built-in I/O is being designed to function as
a higher performance intelligent I/O server to one or more plug-in CPU
boards.
Recommended PC I/O Bus Interface for Pluggable CPU Boards
---------------------------------------------------------
The CPU board PC I/O bus interface consists mainly of two or four dual-port
8K x 8 SRAM's, four cross-CPU interrupts, and custom dual-port arbitration
logic. The intent is to use SRAM ring buffers in an interrupt-driven I/O
scheme. Two SRAM's are used when the CPU has a 16 bit external data bus and
four SRAM's are used when the CPU has a 32 bit external data bus. The data
path on the PC I/O bus side is always 8 bits.
This interface is simple, fast, and inexpensive. This interface is easily
implemented independent of choice of CPU. Its use facilitates a standardized
method for interfacing and communicating with the pluggable CPU boards. Due
to its simplicity any CPU board using this interface is also easily interfaced
and embedded in a custom hardware environment.
CPU Board Hardware Features
---------------------------
- NS32016/NS32C016 MPU microprocessor unit
- NS32081 FPU floating point unit
- NS32082 MMU memory management unit
- NS32202 ICU interrupt control unit
- NS32201/NS32C201 TCU timing control unit
- Dip Switch readable dip switch register for configuration
- 2 EPROM's up to 512k-bit devices
is hardware mapped into two address spaces so that
after startup the eprom can be switched out of lower
memory.
- DRAM Memory: 2MB using 256k x 9 SIMM's
8MB using 1MB x 9 SIMM's
N74F765 DRAM controller
- DRAM parity: byte level parity
errors reported via CPU interrupt
programmable enable/disable parity interrupt
parity error address is captured
- dual-port SRAM ( 2 x 8K x 8) and cross-CPU interrupt PC I/O bus
interface. (PCIOB implementation - refer to separate PCIOB
specifications document)
The CPU board will support the 15 MHZ MPU, FPU, and TCU. However, the
fastest NS32082 MMU is a 10 MHZ version, so virtual memory systems are
limited to 10 MHZ operation. Operation without the MMU allows a 15 MHZ
system. Of course, slower chips will work fine, too.
Two other CPU boards are being considered for design. One would be based
on the NS32CG16 MPU and NS32081 FPU while the other would be based on the
NS32532 MPU and NS32381 FPU. These CPU boards would be architecturally
consistent with the design of this NS32016 CPU board. For the NS32532 MPU
version the DRAM memory design would likely incorporate odd/even 32-bit word
interleave and DRAM static column access so that an external cache memory
would not be needed.
Regarding Reproduction and Distribution of This Document
--------------------------------------------------------
(c) Copyright 1988 by Steven M. Ward ward@cfa.harvard.edu
All rights reserved. ...harvard!cfa!ward
Permission is hereby granted by the author to reproduce and distribute
this document for non-profit, non-commercial purposes on the condition that
this document be completely and faithfully reproduced without any
modification, including the copyright notices and this document section.