david@marvin.jpl.oz.au (01/02/91)
One trick for DRAM on the CG160, is to connect one of the timer outputs to the DMA req line. Then prog the DMA channel for cyclic operation, and the timer for 16 uS output pulses. Once programmed, must wait ?? cycles for the DRAM to initialise internally, then go for it. Cost is 1 of the 2 DMA channels, and 1 of the 3 timers. I've had a good look at the data sheet, but until done, can only say it "seems" possible. Certainly cheaper than any other solution, slows the CPU very little, and solves all the arbitration problems using on-chip logic. The external logic (PAL/EPLD/FPGA/...) should detect the DRAM request with DACK set as a refresh cycle, and do a RAS on all banks, with no CAS. If only a single bank of RAM, then treat as a normal cycle. Because a Refresh cycle can be faster than a normal cycle, special handling of refresh cycles can optimise performance, but seeing that this is a "for-cheap" DRAM controller, and the savings would be minimal, who cares. PS. Same goes for the GX320 .......................................................... "You learn a lot as you go thru life, but not usually what you expected" .......................................................... David Magnay mail david@marvin.jpl.oz.au Boral Elevators was: Johns Perry Lifts 45 Wangara Road, Cheltenham 3192 phone (03) 584-3311 Victoria, Australia O/seas +61 3 584 3311