george@wombat.bungi.COM (George Scolaro) (03/26/91)
I assume that the code that is being executed in ram is the following: reset: br reset1a br scsi reset1a:.byte 0x6d,0xa6,0x08,0xf0 # configure for data cache off movd $(SECOND/1000000)*200,r1# get 200 microsecond delay acbd -1,r1,. movd $0xfffffe00,r7 # point to ICU movb $0x15,22(r7) # set up refresh movqb $0,16(r7) movb $6,24(r7) movqb 0,25(r7) movqb -1,19(r7) # set up a 1 in all outputs ^ This maintains a high on the SWAP signal from the ICU. After reset this signal is an input (before we program it as an output), a pullup resistor ensures that it is high until programmed as an output. movqb 0,20(r7) # set as all I/O movqb -2,21(r7) # g0 as output br reset1+codesp # .byte 0x6d,0xa6,0x0e,0xf0 # Lock data cache reset1: movqb -2,19(r7) # kill rom at zero, swap RAM ^ Note that this instruction clears the SWAP signal coming from the ICU. This signal causes the DRAM to appear at 0H and the EPROM to only appear at it's high memory location. The following is extracted from the DEC32 PLD device. Note how the SWAP signal changes the address locations of the EPROM and DRAM. Pin [1..5] = [a31..27] ; /* 32532 addresses */ Pin 6 = swap ; /* swap dram & eprom */ Pin 7 = a08 ; /* address for int/nmi */ Pin 8 = !ioinh ; /* i/o inhibit */ Pin 9 = !conf ; /* confirmed bus cycle */ Pin 11 = nc0 ; /* */ /** Outputs **/ Pin 12 = !iodec ; /* i/o device decoded */ Pin 13 = !slows ; /* all the slow peripherals */ Pin 14 = !eprom ; /* eprom select */ Pin 15 = !dram ; /* dram select */ Pin 16 = !scsi ; /* scsi select */ Pin 17 = !icu ; /* icu select */ Pin 18 = !duart ; /* duart select */ Pin 19 = !slow ; /* slow device, needs wait states */ /** Declarations and Intermediate Variable Definitions **/ field memadr = [a31..27, a08]; /** Logic Equations **/ dram = memadr:[00000000..07ffffff] & !swap /* normal position */ # memadr:[08000000..0fffffff] & swap; /* at power up */ eprom = memadr:[0..7ffffff] & conf & swap /* at power on */ # memadr:[10000000..17ffffff] & conf; /* normally */ The 'normal' position is when SWAP is cleared to a low. Note that though the DRAM 'moves' from a high location to a low location, the EPROM is always present at the high location (it would be tricky to jump to it if it wasn't there!). The EPROM 'disappears' from the low location when SWAP is cleared to a low, and the DRAM appears there in its place. best regards, -- George Scolaro george@wombat.bungi.com [37 20 51 N / 122 03 07 W]