edlee@chinet.chi.il.us (Edward Lee) (07/16/89)
In article <1657@csm9a.UUCP> kamann@csm9a.UUCP (kamann) writes: >Is the Atari REALLY accessing X megabytes? As I recall most architectures >nowadays are built around a page-swapping facility, even IBM. Perhaps this is true. Perhaps the number of machines that use page- swapping outnumber the number of machines that do not. But for the past two years, I have regularly read flames every few months from other programmers complaining about Intel's segmented architectures in the 8088, 8086 chips. The 68000-based Atari computers can definitely address more than 8 megabytes of memory without page-swapping due to the fact that the 68000 CPUs have 32-bit registers. >Now, I know that IBM is designed around the concept of a 64k paging >area (or the XTs were anyway). So I think it would be safe to say >that an IBM only has 64k addressable also, or is it?!? Intermediate conclusions based on incomplete evidence tend to be transitory. It is safe to say that IBM PC-compatibles using the 8088 or 8086-style of memory handling have a maximum LINEAR addressable memory of 64KB. However, strictly speaking, IBM PC-compatibles generally have more than 64KB of addressable memory (note the absence of LINEAR). >Now, is the Amiga/Atari designed around the same concept? This question is ambiguous, with the ambiguity centering around the word SAME. >I wasn't aware that they had 20 bit buses, but there is still a limitation >to the amount of memory you can actually address, even BIG machines use >page swapping mechanisms and virtual memory. The width of a data bus does not by itself limit the amount of memory a CPU can address. You could have a computer with a 1 bit bus and a 16 bit CPU and still have the computer linearly address 64KB of memory, though the bus would be slow (serial). Unix and Vax-like computers use page swapping because they have memory protection, i.e. some amount of protection from memory over-runs by different processes. They may also be physically limited by the hardware architecture. Generally, virtual memory is any memory that is both based on non-semiconductor media (e.g. magnetic disks, optical disks, holographic plates) and is addressed as if it were CPU memory. Virtual memory is generally cheaper and larger -- but slower -- than comparable physical memory, so virtual memory is used for largely economical reasons. The counterpart to virtual memory is virtual disk, which is CPU memory used as if it were magnetic disk memory (i.e. RAMdisk). -Ed L (A student, looking for a summer job.)
kamann@csm9a.UUCP (kamann) (07/18/89)
In article <8958@chinet.chi.il.us>, edlee@chinet.chi.il.us (Edward Lee) writes: > In article <1657@csm9a.UUCP> kamann@csm9a.UUCP (kamann) writes: > > >Now, I know that IBM is designed around the concept of a 64k paging > >area (or the XTs were anyway). So I think it would be safe to say > >that an IBM only has 64k addressable also, or is it?!? > > Intermediate conclusions based on incomplete evidence tend to be > transitory. It is safe to say that IBM PC-compatibles using the 8088 > or 8086-style of memory handling have a maximum LINEAR addressable memory > of 64KB. However, strictly speaking, IBM PC-compatibles generally have > more than 64KB of addressable memory (note the absence of LINEAR). > Then would it not also be safe to say that the TI "generally" has more than 32k of addressable memory? Although the architecture is not there, something along these lines could be developed from a software standpoint. In addition, the TI has 64k on it once the memory expansion is hooked up, and it is all addressable, although not LINEAR. I guess it comes down to a definition of terms. > > Unix and Vax-like computers use page swapping because they have memory > protection, i.e. some amount of protection from memory over-runs by > different processes. They may also be physically limited by the > hardware architecture. > To a point they are limited by the hardware. Most machines of this size have on the order of 4GB of memory, but will only address Megabytes for any given process (and YES! That is virtual). Just for information, DEC VAX has a 32-bit bus. ============================================================================== Keith Amann | "WIZARD in training! GURU wanna be!" Student Consultant | Colorado School of Mines | BITNET: KAMANN@MINES Computing Center | UUCP: ...!isis!csm9a!kamann Golden, CO 80401 (303)273-3430 | INTERNET: kamann@csm9a.colorado.edu ---------------------------------------------------------------------------- Disclaimer: The thoughts and views discussed above are my own, no one elses! ==============================================================================
edlee@chinet.chi.il.us (Edward Lee) (07/19/89)
In article <1664@csm9a.UUCP> kamann@csm9a.UUCP (kamann) writes: [....] > would it not also be safe to say that the TI "generally" has more than >32k of addressable memory? It would be safe to say that the TMS9900 in the TI-99/4A can always address more than 32KB of addressable memory. The memory can be addressed, but it might not be there. The TI-99/4A computer has a 16-bit CPU and an 8 bit data bus. The 16 bit word length of the TMS9900 allows it to linearly address 64KB of memory. Incidentally, I programmed in TMS9900 assembly language when I was fifteen or sixteen years old and believe that the TMS9900 in the TI-99/4A operates at a clock frequency of 10Mhz instead of 12Mhz, as has been previously claimed by someone else in this newsgroup. > Although the architecture is not there, something >along these lines [of addressing more than 64KB of memory] >could be developed from a software standpoint. [Agreed.] In addition, >the TI has 64k on it once the memory expansion is hooked up, and it is all >addressable, although not LINEAR. [Agreed, but it should be mentioned >that there is non-CPU RAM in the form of GROM/GRAM (TI's own proprietary >memories).] I guess it comes down to a definition of terms. Well, I think we have agreed on using the term LINEAR to describe memory that is accessed by a CPU without memory bank-switching (or swapping, or paging, if you prefer). The TI Extended BASIC cartridge version 1.10 has around 38KB of firmware in it, but 38KB is an unusual size for computer memories. So, I suspect that the TI Extended BASIC cartridge bank-switches firmware to the 8KB (? It's been a while) area of CPU RAM reserved for cartridge memory as it is needed. I believe the same for the Tunnels of Doom cartridge. Someone please correct me if I am wrong about these particulars. Paul Charlton? -Ed L edlee@chinet.chi.il.us
young@pur-ee.UUCP (Mike Young) (07/20/89)
In article <8998@chinet.chi.il.us> edlee@chinet.chi.il.us (Edward Lee) writes: > The TI Extended BASIC cartridge version 1.10 has around 38KB of firmware in >it, but 38KB is an unusual size for computer memories. So, I suspect that the >TI Extended BASIC cartridge bank-switches firmware to the >8KB (? It's been a while) area of CPU RAM reserved for cartridge >memory as it is needed. I believe the same for the Tunnels of Doom >cartridge. Someone please correct me if I am wrong about these >particulars. Paul Charlton? > How about: 3 GROMs @ 6k = 18k 1 16k ROM = 16k 1 4K RAM = 4k ______ 38k ( this is only a slightly educated guess, based on the examination of other TI cartridges. Your mileage may vary. ) Note there's no need for bank switching here. The generic TI peripherals and firmware know nothing about paging, banking, swapping, etc., as far as I've been able to determine. > >-Ed L >edlee@chinet.chi.il.us Mike Young Purdue Univ. EE Dept. young@ecn.purdue.edu ...!pur-ee!young
mr2w+@andrew.cmu.edu (Michael F. Riccio) (07/20/89)
> Excerpts from ext.nn.comp.sys.ti: 20-Jul-89 Re: Addressable memory Mike > Young@pur-ee.UUCP (1058) > In article <8998@chinet.chi.il.us> edlee@chinet.chi.il.us (Edward Lee) > writes: > > The TI Extended BASIC cartridge version 1.10 has around 38KB of > firmware in > >it, but 38KB is an unusual size for computer memories. So, I suspect > that the > >TI Extended BASIC cartridge bank-switches firmware to the > >8KB (? It's been a while) area of CPU RAM reserved for cartridge > >memory as it is needed. I believe the same for the Tunnels of Doom > >cartridge. Someone please correct me if I am wrong about these > >particulars. Paul Charlton? > > > How about: > 3 GROMs @ 6k = 18k > 1 16k ROM = 16k > 1 4K RAM = 4k > ______ > 38k > ( this is only a slightly educated guess, based on the examination > of other TI cartridges. Your mileage may vary. ) Note there's no need for > bank switching here. The generic TI peripherals and firmware know nothing > about paging, banking, swapping, etc., as far as I've been able to > determine. > > > >-Ed L > >edlee@chinet.chi.il.us > Mike Young > Purdue Univ. EE Dept. > young@ecn.purdue.edu > ...!pur-ee!young Try: 4 GROMS (@6K each) 24K 12K ROM 12K --- 36K They lied about the other 2K. The 12K of ROM fits in the 8K space from >6000 to >7FFF. This is accomplished by bank switching the lower 4K (>7000 - >7FFF). Most Atari carts also have 16K of ROM and bank switch the entire 8K. The back switching is accomplished by writing to the ROM. Writing to >6000, >6004, >6008, etc pages in bank 0, and writing to >6002, >6006, >600A, etc pages in back 1. This is all described in great detail in the manual that comes with the Gram Kracker. Just FYI, here is the 4A memory map: >0000 - >1FFF (8K) ROM Op-Sys (GPL Interpreter, Math libraries, etc) >2000 - >3FFF (8K) RAM Memory Expansion >4000 - >5FFF (8K) Peripheral ROM (DSR device drivers, mapped in as needed.) >6000 - >7FFF (8K) Cartridge ROM (or RAM) >8000 - >82FF (.75K) Not used >8300 - >83FF (.25K) Scratchpad RAM (0 wait state) >8400 - >9FFF (7K) Memory Mapped I/O (Not real memory - ports) >A000 - >FFFF (24K) RAM Memory Expansion 64K total directly accessible memory. Through the memory mapped I/O, you can address 8 banks of 64K of GROM, 16K Video RAM, speech, and sound. Through the 4Kbits of CRU, you can map in unlimited banks of DSR ROM and/or RAM. Mike Riccio Com-Link Enterprises mr2w+comlink@andrew.cmu.edu ...!harvard!andrew.cmu.edu!mr2w+comlink
chuckn@psueea.uucp (Chuck Neal) (07/21/89)
In article <8998@chinet.chi.il.us> edlee@chinet.chi.il.us (Edward Lee) writes: >swapping, or paging, if you prefer). The TI Extended BASIC cartridge >version 1.10 has around 38KB of firmware in it, but 38KB is an >unusual size for computer memories. So, I suspect that the >TI Extended BASIC cartridge bank-switches firmware to the >8KB (? It's been a while) area of CPU RAM reserved for cartridge >memory as it is needed. I believe the same for the Tunnels of Doom >cartridge. Someone please correct me if I am wrong about these >particulars. Paul Charlton? TI Extended BASIC has 16KB of bank switched ROM and 4 6KB GROMS. Chuck Neal (chuckn@jove.cs.pdx.edu) Former treasurer of PUNN (Portland Users of Ninety Nine) Try our BBS (503) 233-6804