maji@uwav1.u.washington.edu (Ma Ji from UW physics) (10/13/89)
Is anyone out there in this netland knows about pin assignment for the game port or edge slot on TI99/4A, or the pin out for TMS9900 cpu? I would appre -ciate if you can tell me directly or tell me where I can find. -- +-----------------------------------------------------------------------------+ | E-mail : maji@vax1.acs.washington.edu | | phone : (206)-634-1357 (home) | | address: Dept of Phys, FM-15, Univ of Washington, Seattle, WA 98195 | +-----------------------------------------------------------------------------+
waw103@tijc02.UUCP (Alan Watson ) (10/18/89)
*** THIS LINE LEFT INTENTIONALLY NON-BLANK *** >maji@uwav1.u.washington.edu writes: > port or edge slot on TI99/4A, or the pin out for TMS9900 cpu? I tried email but it came back so I'm posting this for all of you in the US. Ah yes, the tms9900. I have used it before on several projects. Great for context switching applications since you can change your workspace pointer and get a whole new set of registers, no need to push or pop! The TMS 9900 pin assignments: (* indicates active low) +--------------+ Vbb -| 1 64 |- HOLD* Vcc -| 2 63 |- MEMEN* WAIT -| 3 62 |- READY LOAD* -| 4 61 |- WE* HOLDA -| 5 60 |- CRUCLK RESET* -| 6 59 |- Vcc IAQ -| 7 58 |- nc phi1 -| 8 57 |- nc phi2 -| 9 56 |- D15 A14 -| 10 55 |- D14 A13 -| 11 54 |- D13 A12 -| 12 53 |- D12 A11 -| 13 52 |- D11 A10 -| 14 51 |- D10 A9 -| 15 50 |- D9 A8 -| 16 49 |- D8 A7 -| 17 48 |- D7 A6 -| 18 47 |- D6 A5 -| 19 46 |- D5 A4 -| 20 45 |- D4 A3 -| 21 44 |- D3 A2 -| 22 43 |- D2 A1 -| 23 42 |- D1 A0 -| 24 41 |- D0 phi4 -| 25 40 |- Vss Vss -| 26 39 |- nc Vdd -| 27 38 |- nc phi3 -| 28 37 |- nc DBIN -| 29 36 |- IC0 CRUOUT -| 30 35 |- IC1 CRUIN -| 31 34 |- IC2 INTREQ* -| 32 33 |- IC3 +--------------+ Notes: A0 - A14: address bus. A0 = MSB. 3 - state bus provides memory address vector when MEMEN* is active and the I/O - bit addresses and external-instaruction addresses when MEMEN* is inactive. High impedance when HLODA is active. D0 - D15: data bus. D0 = MSB. This bus transfers data to and from the external-memory system when MEMEN* is active. Vbb: -5 volts nominal Vcc: 5 volts nominal (2 and 59 must be connected in parallel) Vdd: 12 volts nominal Vss: ground reference phi1-phi4: clocks (input) DBIN: Data bus in. (output) MEMEN*: Memory Enable (output) WE*: Write Enable (output) CRUCLK: When active (high) data appears on the CRUOUT line for external interface logic. (output) CRUIN: CRU data in (CRU data is bit I/O) (input) CRUOUT: CRU data out (output) INTREQ*: Interrupt request (input) IC0-IC4: Interrupt codes (input) HOLD*: delay for memory set-up (input) HOLDA: hold acknowledge (output) READY: memory ready for read/write (input) WAIT: Wait state indicator (output) IAQ: Instruction acquisition flag (output) LOAD*: execute non-maskable interrupt (input) RESET*: reset (input) This data comes from the Texas Instruments 9900 Family Systems Design data book, first edition, copyrighted 1978, Texas Instruments. This book contains AC and DC characteristics along with chapters on software design and the 9900 family instruction set. In general, all sorts of good stuff. I presume it is still pertinent. The book is ISBN 0-89512-026-7, Library of Congress Catalog Number 78-058005 but I doubt you'd be able to find it anywhere. TI does have a Customer Response Center which will try to assist any customer with a question or need for information. They have a toll-free line, 800-232-3200, as well as a regular line, 214-995-6611. You might even get some info on the 99/4a port pinouts. DISCLAIMER: This information is probably correct but it may not be. I may have even unintentionally left out something important. I work for TI but I have nothing to do with their semiconductor business. Alan Watson waw103@rti!tijc02 Texas Instruments - Process Automation Systems Johnson City, TN