BIW109@URIMVS.BITNET (09/09/88)
I have a question on the timing of the 6502. Which requires more
time, an LDA, or an STA? The reason that I ask is that I am working
on an interfacing project, and am running into problems. I think that
the problem might be caused by too much delay time in the interface
its self. The problem is that I am able to read from an external port
(in this case, an A/D converter) with 100% accuracy, but I an unable to
write to another port (a D/A converter made from an 8-bit latch and an
R-2R resistor ladder). Writes to the D/A converter are sucessful only
about 10% of the time. The interface circuit introduces the same delay
before activating each port. I think that I am able to read ok because
on the fact that the cpu allows at least 250ns for the memory (or what
ever is on the bus) to respond. Can anyone tell me how much time the
cpu allows for memory (or what ever) to latch a byte from the bus?
Ray C
biw109@urimvs <----- 'New and improved' user number!!
phr140 will be deleted next week..rbrown@svax.cs.cornell.edu (Russell Brown) (09/10/88)
In article <8809091641.AA15253@ucbvax.Berkeley.EDU> BIW109@URIMVS.BITNET writes: > > I have a question on the timing of the 6502. Which requires more >time, an LDA, or an STA? The reason that I ask is that I am working >on an interfacing project, and am running into problems. I think that >the problem might be caused by too much delay time in the interface >its self. The problem is that I am able to read from an external port >(in this case, an A/D converter) with 100% accuracy, but I an unable to >write to another port (a D/A converter made from an 8-bit latch and an >R-2R resistor ladder). Writes to the D/A converter are sucessful only >about 10% of the time. The interface circuit introduces the same delay >before activating each port. I think that I am able to read ok because >on the fact that the cpu allows at least 250ns for the memory (or what >ever is on the bus) to respond. Can anyone tell me how much time the >cpu allows for memory (or what ever) to latch a byte from the bus? > The timing for reading and writing bytes to memory is roughly the same. In either a store or a fetch, one memory cycle is used (during the first part of the cycle, phase-1, an address is placed on the bus by the processor. Devices connected to the bus decide during this time if they are being addressed; if the chip enable is set, then depending on the state of the R/W' line, the enabled device either stores what it finds on the data bus during phase-2, or outputs information onto the bus). There are a number of signals which must be dealt with properly; if you are having difficulty on writes, you might check that data from the bus is getting clocked into your latch during phase-2 proper (i. e. the information actually has time to settle before you read it -- this would be a case of reading into the latch too quickly, not too slowly. Note that a latch is sufficiently speedier than memory that the speed of your interface should not be a problem). My information is a little stale; also tinged with M6801 terms. I hope this is of some use to you. Russell g. Brown
ehs@jumbo.dec.com (Ed Satterthwaite) (09/10/88)
One other thought.
When I opened up my 800 a while ago, I found a Rockwell 6502B. For write
data, Rockwell's specs for the B version provide a minimum hold time of 15
ns. from fall of phi2 (end of phase-2). These timings are at the
processor chip pins.
If you are using a flow-through latch ('373 or similar), the data has to
be valid when the latch closes and has to remain so for, e.g., at least 20
ns (TI's specs for 74LS373). In most designs, the write strobe is a gated
phi2. So things are already problematical. They will probably work
because the capacitance of the data bus is working for you and most TTL
parts I've encountered are considerably better than their specs, but ...
I have seen designs (gated phi2) in which there are more logic delays on
the write strobe than buffering delays in the data path. This could push
things over the edge (data corrupted before latch closes) and account for
the marginal operation you observe. If I recall correctly (I don't have
the schematics at hand), the system phi2 on an 800 might already be
leading the 6502's phi2 by the difference between two gate delays. The
XLs and XEs actually use a customized 6502, which handles phi2 differently
and might be better or worse. If you are right on the edge, going to a
74F latch might bail you out (hold time on a 74F373 is 3 ns, for example).
Bypass generously. Also, hold times for edge-triggered flip-flops are
typically lower than for latches, but you don't get the flow-through and
you can't use the leading edge of phi2 (data not speced to be there yet).
Finally, I have seen MOS parts with internal latches that have very long
hold times compared to TTL. If you're using such a part, simple
interfacing might just be incompatible with reliable operation.
I hope that some of this helps and that none of it is too misleading --
it's been a long time since I've looked at my Atari. I suggest investing
in some schematics and data books if you can find them, then checking the
timing margins on all the relevant signals.
Ed Satterthwaite
{...}!decwrl!ehs
ehs@src.DEC.COMOrdania-DM@cup.portal.com (09/11/88)
Here are the timing specs for LDA and STA:
opcode mode cycles
LDA imm 2
" abs 4
" z-page 3
" (ind,x) 6
" (ind),y 5*
" zpage,x 4
" abs,x 4*
" abs,y 4*
STA abs 4
" z-page 3
" (ind,x) 6
" (ind),y 5*
" zpage,x 4
" abs,x 4*
" abs,y 4*
* Add 1 cycle if page boundary is crossed.
As you can see, they take the same amount of time regardless of the opcode,
the timing is dependent on the addressing mode, and where the data to be
addressed is located (within a page as opposed to across several pages).
I don't know if this will help you much, but it is what you asked for.chasm@killer.DALLAS.TX.US (Charles Marslett) (09/12/88)
The question was asked: "What is the difference between the time a LDA instruction takes, and the time a STA takes?" It depends on the indexing, zero page stuff, etc., but in general, a store takes one clock cycke longer than the load, add, or, and, etc. Charles Marslett chasm@killer.dallas.tx.us