BIW109@URIMVS.BITNET (09/16/88)
The interface connects to the computer through the cart. port.
it uses the 7 low order address lines, and the CCNTL line for control
(addresses $D500 to $D57F are decoded). I used a design like this
because i want to build an interface into which cards can be plugged
into. The decoding logic works like this: A0-A3 are fed into one
74154 (4 to 16 line decoder), A4-A6 are fed into another one. Both
are enabled by the CCNTL (active low) line. All of the outputs of
the 74154's that are used (all on the first, only the first half on the
2nd - its high order input line is grounded) are inverted to obtain
active high strobes. The sixteen outputs from the first 74154 are
fed to 8 44-pin female plug in slots. The 8 outputs from the second
74154 are fed to one slot each (these are used to activate cards in
individual slots. The read/write line is passed to all slots in both
origional and inverted form. This was done so that when a particular
address on a card needs to be activated, a 3-input and gate can be used
(active high strobe) or a 3-input nand gate can be used (active low
strobe). Using this method, a card can be used in any slot, as long
as the program knows which one it is in (the relative addresses within
each slot are the same).
The data latch in question is a 74374 (i think.. I haven't been
home from school to look at it in the past few weeks), and acts on the
rising edge of the pulse. The timing problem that I was intested in
is how long is data valid for once it is placed onto the bus? Since
the latch acts on the rising edge of the strobe, i assumed that the
interface circuit must be taking too long. Since the 74154 is the most
complicated chip in the interface (if I remember correctly, it has at
least 4 or 5 levels of gates in it) I was thinking of using a high
speed version of the chip, assuming I can find one.
I hope this is enough info.. And thanks to anyone who can help..
Ray C
bitnet: biw109@urimvseuloth@dalcsug.UUCP (George Seto) (09/17/88)
In article <8809152000.AA28912@ucbvax.Berkeley.EDU>, BIW109@URIMVS.BITNET writes: >The data latch in question is a 74374 (i think.. I haven't been > home from school to look at it in the past few weeks), and acts on the > rising edge of the pulse. The timing problem that I was intested in > is how long is data valid for once it is placed onto the bus? Since > the latch acts on the rising edge of the strobe, i assumed that the > interface circuit must be taking too long. Since the 74154 is the most > complicated chip in the interface (if I remember correctly, it has at > least 4 or 5 levels of gates in it) I was thinking of using a high > speed version of the chip, assuming I can find one. I don't know for sure, but..... You can get "high" speed versions of the 74374 but I am not sure about the '154 in High Speed versions. I would suggest usage of the HC series of devices, or if you can't find them, LS series. 74LS and 74HC are both faster than standard TTL. LS stands for Low-power Schottky and HC stands for High-speed CMOS devices. There is also a version of the HC called HCT which will work best with TTL devices. As you can see, the both of them should also be lower power than the original TTL devices you have mentioned. I will check on the availability of HC and LS versions of the 74154 and advise tomorrow. > -- ******************************************************************************* * euloth@dalcsug.uucp || Disclaimer: All opinions are my own unless other- * * /\/\/\/\/\/\/\/\/\/\ || wise noted. * ****AKA: Atari Nut*************************************************************
rbrown@svax.cs.cornell.edu (Russell Brown) (09/18/88)
The old Ataris run on the 1.79 MHz 6502B. The 6502 clock setup provides for a two part instruction cycle. Information placed on the bus is supposed to be valid for the duration of the appropriate part of the cycle (address during phi-1, data during phi-2). Phi-1 and phi-2 are approximately equal, each accounting for about 40% of an instruction cycle (with the other 20% taken up by transitions -- phi-1 and phi-2 are nonoverlapping, so there's some space between them). My documentation isn't where I can get at it, so I can't look up whether an instruction cycle takes 1/(1.79MHz) or 2/(1.79Mhz), but if we assume, for the moment, the former, then each phase of the cycle lasts about 223 nanoseconds (if the assumption is incorrect, then the cycle lasts some small integer (perhaps 2) times that long). As I said, this is not the final word, but I have confidence that it is no shorter than this.