BIW109@URIMVS.BITNET (09/22/88)
Sorry I had to reply to the net, but the mailer could not find
your host (ehs@src.dec.com) ....
Received: from MITVMA.MIT.EDU by MITVMA.MIT.EDU (IBM VM SMTP R1.1) with BSMTP id
0232; Sun, 18 Sep 88 14:39:05 EDT
Received: from URIMVS.BITNET by MITVMA.MIT.EDU (Mailer X1.25) with BSMTP id
0231; Sun, 18 Sep 88 14:39:03 EDT
Date: Sun, 18 Sep 88 14:40 EDT
From: BIW109%URIMVS.BITNET@MITVMA.MIT.EDU
To: ehs@src.dec.com
Subject: re: interfacing problem help
I think the CS2 line you describe is the same as the CCNTL line.
I got most of my information from Mapping the Atari (revised edition).
I am using an xl (the dreaded 1200xl, to be exact). All of the storbes
are ANDed or NANDed with the proper r/w signal, I didn't want strobes
being generated by accident.. Where is the phi2 (is this the second
phase of a 2 phase clock?) line that you mentioned? All Mapping the
Atari gives is a pin-out of the cart. port, giving names only for most
pins. If the phi2 is active low, it should be a simple matter to
invert it and and it with the write line, and make this result the
new write line (all strobes that the interface card generates are
active high). If I understand what you said correctly, the purpose
of phi2 is to indicate that the data bus is valid during write to
memory operations. Is this correct?
Thanks for your help!!
Ray Courtois
biw109@urivms