thomas@kuling.UUCP (Thomas H{meenaho) (11/12/86)
In article <90@lmi-angel.UUCP> wsr@lmi-angel.UUCP (Wolfgang Rupprecht) writes: >The NuBus was designed by MIT, and sold to TI. It is quite easy to >interface to from a logic standpoint, since *everything* is >synchronous to the system clock. The whole bus runs on one 96 pin >connector, with the center 32 pins being extra power and grounds for >power hungry cards. The 32-bit address and data lines are muxed, so >you can get by with < 64 address/data buffers per card. The bus >arbitration is distributed on each of the cards, and uses an >inherently fair algorithm. It was truly designed for a multiprocessor >system. It definitely requires much less in terms of bus lines and >support logic to make it work than the other 32 bit addr 32 bit data >busses. All in all a good example of a bus designed by people that >didn't need to make a particular processor look good. Three things about the NuBus I don't like: 1) It allows only 16 slots. 2) It's block transfer mode is awkward compared to the VMEbus one. 3) The boards are HUGE. Ok, when designing complicated boards it is nice to have a huge area at hand but it makes the system big! One other thing I think should be changed is the source of the clock. Currently one board must supply it. This should be included in the backplane, perhaps as a small module on the back. If this is done then no board would be special in the sense of supplying special signals. -- Thomas Hameenaho, Dept. of Computer Science, Uppsala University, Sweden Phone: +46 18 138650 UUCP: thomas@kuling.UUCP (...!{seismo,mcvax}!enea!kuling!thomas)