urip@orcisi.UUCP (01/08/87)
Although it's coming a little late, and some readers may have forgotten the
original article (On Holy Wars and a Plea for Peace by Danny Cohen) by now,
I still hope that my article will get enough audience.
My point is that the Least-Significant-Byte-first camp (LSBians,
pronounced: elesbians) has a more correct way than the Most-Significant-byte-
first (MSBians, pronounced: emesbians), and I am going to try to convince
the MSBians to go my way.
Before I start with the main issue, let me comment about the side issue.
As someone who's native language is Hebrew and also knows some
Arabic from school, I would like to confirm almost everything that was said
in the article and in the responses about the order of digits etc. including
the examples from the Bible and computer terminals in Arabic/Hebrew.
There was a slight inaccuracy about the way numbers are read in Arabic:
Only the units and tens are read the LSBian way, and the rest of
the number is read the MSBian way. For example, the year 1984 is read:
"one thousand nine hundreds four and eighty". Also, for those who don't know,
the digit characters in Arabic are different from the Latin forms, but
in Hebrew they are the same.
The article was written in 1980, and things have changed since then.
Six years are a lifetime in the world of computers, and sentences like:
"I failed to find a Little-Endians' system which is totally consistent"
cannot be left without an objection in 1986 (almost 1987).
The Intel 80*86 micro processors are true, consistent LSBians. They do not
have combined shift operations (the article suggested these as a good criterion
to tell between LSBians and MSBians), but the multiply operation sure leaves
the most significant part of the result in the high register, and the floating
point format is totally consistent with the rest of the data types.
The same is true for the National Series 32000 and I believe that Zilog
is with the LSBians too.
So in the micro processor area, it seems that Motorola 68000
is the only (though major...) MSBian around. Now, is it really as clean
and pure MSBian as claimed in the article? Let me refresh your memory
with a quote from the article:
"Hence, the M68000 is a consistent Big-Endian, except for its bit
designation, which is used to camouflage its true identity.
Remember: the Big-Endians were the outlaws."
The author did not try to claim that the funny floating point format
of the VAX was to camouflage the VAX's true identity, so why should one believe
that the LSBian bit order of the M68000 is because "the Big-Endians were
the outlaws" ? I suspect that the true reason behind the inconsistency
of the M68000 is the fact that only with an LSBian bit order, the value of
bit number 'i' in a word is always equal to
b[i] * 2^i
(where b[i] is 0 or 1 according to bit number 'i', and 2^i is 2 to the power
of i)
and the designers of M68000 wanted to keep this important feature in spite of
the overall MSBian architecture.
There is another difference between LSBian and MSBian memory order that
was not mentioned in the article.
In the LSBian scheme, if a long-word in memory contains a small value,
then a word or a byte in the same memory location still hold the same
value (if the value is small enough to fit into these).
For example, assume we have the value 0x00000002 in a (32 bit) long-word
in memory address 100.
LSB in lower address
address 104 103 102 101 100
+----+----+----+----+
value | 00 | 00 | 00 | 02 |
+----+----+----+----+
Note that a long-word, short word, byte and even nibble at address 100, all
contain value 2.
On the other hand,
MSB in lower address
address 100 101 102 103 104
+----+----+----+----+
value | 00 | 00 | 00 | 02 |
+----+----+----+----+
Note that only a long-word at address 100 contains 2. All the rest contain 0.
This may not seem to be a key issue, but it has some significance in type
conversion as illustrated by the following C program segment:
/*=================================*/
int i;
char ch;
ch = i;
/*=================================*/
The 'int' (assume int is 32 bits) value has to be converted to 'char' or byte.
In LSBian, this conversion is just a simple 'movb' (move byte) instruction
from 'i' to 'ch':
movb i, ch
since both byte and long-word contain the same value.
In MSBian it may involve an expensive bit field instruction (or worse,
shifts and ands). Luckily for the M68000, it is byte addressable, so the
compiler can do the trick and generate:
movb i+3, ch
So it is still a simple machine instruction, but it involves a small trick.
Not clean, but still consistent, as long as we stick to byte addressable
memory.
But what about registers? registers are not byte addressable.
There is only one byte of a register that can be accessed by a 'movb'
instruction. All the other 3 bytes can be accessed only through bit field
instructions (or worse, shifts and ands).
Let's look at another program segment:
/*=================================*/
extern int fgetc();
char ch;
ch = fgetc(file);
/*=================================*/
The C library routine 'fgetc' returns an 'int' result and it has to be
converted to 'char'. Most implementations return function results in
register 0.
Assume that register D0 contains 'int' (32 bits) value 2,
and so does the long-word at address 100.
MSB in lower address
address 100 101 102 103 104
+----+----+----+----+
value | 00 | 00 | 00 | 02 |
+----+----+----+----+
+----+----+----+----+
register D0 | 00 | 00 | 00 | 02 |
+----+----+----+----+
The instructions
movl 100,x
movl D0,x
both move a long-word containing value 0x00000002 to location 'x'.
so
movb 100,x
movb D0,x
both should move a byte containing value 00 to locaion 'x'.
So the code generated for above program segment in a true consistent
MSBian machine would be:
jbsr fgets
movl 24,d1
lsrl d1,d0
movb d0,ch
But in M68000 this is not true. No shift operation is needed because
a 'movb' instruction with a register operand takes the byte that contains 2,
that is, the HIGH address bit, so the compiler can generate a
jbsr fgets
movb d0,ch
In other words, we see that the byte/word/long-word overlap of registers
in the M68000 is implemented according to the more efficient LSBian way!!
Conclusion:
==========
I have shown that there are two aspects in which the LSBian way is more
suitable and more efficent for binary computers. This is in addition
to the argument of easier serial addition and multiplication that was mentioned
in the article (though the latter is balanced, to some extent, by serial
comparison and division).
The main argument left against the LSBians is the more readable MSBian
dump format. I think that in the modern days of optimizing compilers and
symbolic debuggers, dumps are almost an extinct species, and please
let them stay that way.
I don't have any illusions. I don't expect Motorola to change their byte order
after reading my article. I don't even expect users to prefer LSBian
machines just for the sake of beauty and consistency.
But I do hope that some day the LSBian method will prevail (or, maybe,
someone will convince me of the superiority of the MSBian method...).
Uri Postavsky (utcs!syntron!orcisi!urip)
(currently with O.R.C Toronto,
formerly with National Semiconductor Tel Aviv).
From postnews Thu Jan 8 10:22:34 1987
Subject: Byte Order: be reasonable - do it my way...
Newsgroups: comp.sys.m68k,comp.arch,comp.sys.intel
Although it's coming a little late, and some readers may have forgotten the
original article (On Holy Wars and Plea for Peace by Danny Cohen) by now,
I still hope that my article will get enough audience.
My point is that the Least-Significant-Byte-first camp (LSBians,
pronounced: elesbians) has a more correct way than the Most-Significant-byte-
first (MSBians, pronounced: emesbians), and I am going to try to convince
the MSBians to go my way.
Before I start with the main issue, let me comment about the side issue.
As someone who's native language is Hebrew and also knows some
Arabic from school, I would like to confirm almost everything that was said
in the article and in the responses about the order of digits etc. including
the examples from the Bible and computer terminals in Arabic/Hebrew.
There was a slight inaccuracy about the way numbers are read in Arabic:
Only the units and tens are read the LSBian way, and the rest of
the number is read the MSBian way. For example, the year 1984 is read:
"one thousand nine hundreds four and eighty". Also, for those who don't know,
the digit characters in Arabic are different from the Latin forms, but
in Hebrew they are the same.
The article was written in 1980, and things have changed since then.
Six years are a lifetime in the world of computers, and sentences like:
"I failed to find a Little-Endians' system which is totally consistent"
cannot be left without an objection in 1986 (almost 1987).
The Intel 80*86 micro processors are true, consistent LSBians. They do not
have combined shift operations (the article suggested these as a good criterion
to tell between LSBians and MSBians), but the multiply operation sure leaves
the most significant part of the result in the high register, and the floating
point format is totally consistent with the rest of the data types.
The same is true for the National Series 32000 and I believe that Zilog
is with the LSBians too.
So in the micro processor area, it seems that Motorola 68000
is the only (though major...) MSBian around. Now, is it really as clean
and pure MSBian as claimed in the article? Let me refresh your memory
with a quote from the article:
"Hence, the M68000 is a consistent Big-Endian, except for its bit
designation, which is used to camouflage its true identity.
Remember: the Big-Endians were the outlaws."
The author did not try to claim that the funny floating point format
of the VAX was to camouflage the VAX's true identity, so why should one believe
that the LSBian bit order of the M68000 is because "the Big-Endians were
the outlaws" ? I suspect that the true reason behind the inconsistency
of the M68000 is the fact that only with an LSBian bit order, the value of
bit number 'i' in a word is always equal to
b[i] * 2^i
(where b[i] is 0 or 1 according to bit number 'i', and 2^i is 2 to the power
of i)
and the designers of M68000 wanted to keep this important feature in spite of
the overall MSBian architecture.
There is another difference between LSBian and MSBian memory order that
was not mentioned in the article.
In the LSBian scheme, if a long-word in memory contains a small value,
then a word or a byte in the same memory location still hold the same
value (if the value is small enough to fit into these).
For example, assume we have the value 0x00000002 in a (32 bit) long-word
in memory address 100.
LSB in lower address
address 104 103 102 101 100
+----+----+----+----+
value | 00 | 00 | 00 | 02 |
+----+----+----+----+
Note that a long-word, short word, byte and even nibble at address 100, all
contain value 2.
On the other hand,
MSB in lower address
address 100 101 102 103 104
+----+----+----+----+
value | 00 | 00 | 00 | 02 |
+----+----+----+----+
Note that only a long-word at address 100 contains 2. All the rest contain 0.
This may not seem to be a key issue, but it has some significance in type
conversion as illustrated by the following C program segment:
/*=================================*/
int i;
char ch;
ch = i;
/*=================================*/
The 'int' (assume int is 32 bits) value has to be converted to 'char' or byte.
In LSBian, this conversion is just a simple 'movb' (move byte) instruction
from 'i' to 'ch':
movb i, ch
since both byte and long-word contain the same value.
In MSBian it may involve an expensive bit field instruction (or worse,
shifts and ands). Luckily for the M68000, it is byte addressable, so the
compiler can do the trick and generate:
movb i+3, ch
So it is still a simple machine instruction, but it involves a small trick.
Not clean, but still consistent, as long as we stick to byte addressable
memory.
But what about registers? registers are not byte addressable.
There is only one byte of a register that can be accessed by a 'movb'
instruction. All the other 3 bytes can be accessed only through bit field
instructions (or worse, shifts and ands).
Let's look at another program segment:
/*=================================*/
extern int fgetc();
char ch;
ch = fgetc(file);
/*=================================*/
The C library routine 'fgetc' returns an 'int' result and it has to be
converted to 'char'. Most implementations return function results in
register 0.
Assume that register D0 contains 'int' (32 bits) value 2,
and so does the long-word at address 100.
MSB in lower address
address 100 101 102 103 104
+----+----+----+----+
value | 00 | 00 | 00 | 02 |
+----+----+----+----+
+----+----+----+----+
register D0 | 00 | 00 | 00 | 02 |
+----+----+----+----+
The instructions
movl 100,x
movl D0,x
both move a long-word containing value 0x00000002 to location 'x'.
so
movb 100,x
movb D0,x
both should move a byte containing value 00 to locaion 'x'.
So the code generated for above program segment in a true consistent
MSBian machine would be:
jbsr fgets
movl 24,d1
lsrl d1,d0
movb d0,ch
But in M68000 this is not true. No shift operation is needed because
a 'movb' instruction with a register operand takes the byte that contains 2,
that is, the HIGH address bit, so the compiler can generate a
jbsr fgets
movb d0,ch
In other words, we see that the byte/word/long-word overlap of registers
in the M68000 is implemented according to the more efficient LSBian way!!
Conclusion:
==========
I have shown that there are two aspects in which the LSBian way is more
suitable and more efficent for binary computers. Even an MSBian machine
like M68000 is LSBian in these aspects. This is in addition
to the argument of easier serial addition and multiplication that was mentioned
in the article (though the latter is balanced, to some extent, by serial
comparison and division).
The main argument left against the LSBians is the more readable MSBian
dump format. I think that in the modern days of optimizing compilers and
symbolic debuggers, dumps are almost an extinct species, and please
let them stay that way.
I don't have any illusions. I don't expect Motorola to change their byte order
after reading my article. I don't even expect users to prefer LSBian
machines just for the sake of beauty and consistency.
But I do hope that some day the LSBian method will prevail (or, maybe,
someone will convince me of the superiority of the MSBian method...).
Uri Postavsky (utcs!syntron!orcisi!urip)
(currently with O.R.C Toronto,
formerly with National Semiconductor Tel Aviv).mwm@cuuxb.UUCP (01/11/87)
In article <760@orcisi.UUCP> urip@orcisi.UUCP writes: >My point is that the Least-Significant-Byte-first camp (LSBians, >pronounced: elesbians) has a more correct way than the Most-Significant-byte- >first (MSBians, pronounced: emesbians), and I am going to try to convince >the MSBians to go my way. >... >"Hence, the M68000 is a consistent Big-Endian, except for its bit >designation, which is used to camouflage its true identity. >Remember: the Big-Endians were the outlaws." > >The author did not try to claim that the funny floating point format >of the VAX was to camouflage the VAX's true identity, so why should one believe >that the LSBian bit order of the M68000 is because "the Big-Endians were >the outlaws" ? I suspect that the true reason behind the inconsistency >of the M68000 is the fact that only with an LSBian bit order, the value of >bit number 'i' in a word is always equal to > > b[i] * 2^i > >(where b[i] is 0 or 1 according to bit number 'i', and 2^i is 2 to the power >of i) >and the designers of M68000 wanted to keep this important feature in spite of >the overall MSBian architecture. The bit notation is strictly notational, and has no bearing on the operation of the cpu. One could go entirely through any MC68000 book and replace the bit-numbers appropriately throughout. Bit notation (what way you number which bits) has no relation to byte ordering. I could number my bits: 13579BDF2468ACE 000000000000001 to represent the number 1 if I so chose. Saying that byte ordering that proceeds in the opposite direction to bit ordering is some how "inconsistent" is part of your argument, I would maintain that it is moot. > [ long disscussion of how in LSBian machines, a movebyte 2,x and a > movelong 2,x generate the same bits at location x] > >This may not seem to be a key issue, but it has some significance in type >conversion as illustrated by the following C program segment: > >{int i; char ch; ch = i;} > >The 'int' (assume int is 32 bits) value has to be converted to 'char' or byte. >In LSBian, this conversion is just a simple 'movb' (move byte) instruction >from 'i' to 'ch': > > movb i, ch > >since both byte and long-word contain the same value. > >In MSBian it may involve an expensive bit field instruction (or worse, >shifts and ands). Luckily for the M68000, it is byte addressable, so the >compiler can do the trick and generate: > > movb i+3, ch > >So it is still a simple machine instruction, but it involves a small trick. Actually, what should be done, in general, is something similar to the VAX trick of having a conversion instruction, and do a cvt_lb i,ch Unfortunately, in the 68000 the type-conversion (sign extension/truncation) operations only work between registers, and one is forced to resort to kluges like mov.b i+3,ch in order to do the job efficiently. >Not clean, but still consistent, as long as we stick to byte addressable >memory. > >But what about registers? registers are not byte addressable. >There is only one byte of a register that can be accessed by a 'movb' >instruction. All the other 3 bytes can be accessed only through bit field >instructions (or worse, shifts and ands). This is true of big-endian and little-endian machines which are byte addressable.... >Let's look at another program segment: > > {extern int fgetc(); char ch; ch = fgetc(file);} > >The C library routine 'fgetc' returns an 'int' result and it has to be >converted to 'char'. Most implementations return function results in >register 0. > >Assume that register D0 contains 'int' (32 bits) value 2, >and so does the long-word at address 100. > > MSB in lower address > >address 100 101 102 103 104 > +----+----+----+----+ >value | 00 | 00 | 00 | 02 | > +----+----+----+----+ > +----+----+----+----+ >register D0 | 00 | 00 | 00 | 02 | > +----+----+----+----+ > >The instructions > > movl 100,x > movl D0,x > >both move a long-word containing value 0x00000002 to location 'x'. >so > movb 100,x > movb D0,x > >both should move a byte containing value 00 to locaion 'x'. Okay so far, both big endian and little endian machines do this; so long as the definition of "Location x" includes a *type*. Whether that type is a 17 bit wide field or a 1 byte wide feild, in either machine, locations need types to make them consistent. Type conversion could even be implemented to generate an exception on truncation of signifigant bits, and to sign extend appropriately. >So the code generated for above program segment in a true consistent >MSBian machine would be: > > jbsr fgets > movl 24,d1 > lsrl d1,d0 > movb d0,ch Huh? Once again you are defining "consistent" to suit your argument against MSBian machines. > >But in M68000 this is not true. No shift operation is needed because >a 'movb' instruction with a register operand takes the byte that contains 2, >that is, the HIGH address bit, so the compiler can generate a > > jbsr fgets > movb d0,ch Once again you miss the fact that the longword at location x is different from the character at location x. (This is, incidentally, a register-based type conversion, treating d0 first as a long and then as a character, as per my discussion above. The code should read: jsbr fgets cvt_lb d0,ch It just so happens that a movb on a long word *does* convert long to byte.) > >In other words, we see that the byte/word/long-word overlap of registers >in the M68000 is implemented according to the more efficient LSBian way!! > Wait a minute. First you claim that the MC68000 is MSBian, but that its *registers* are LSBian???? What does byte order in memory have to do with registers??? Are you saying that the 68000 should load bytes into the high order bits of a register rather than the low order bits in order to be "consistent"? > >Conclusion: >========== > >I have shown that there are two aspects in which the LSBian way is more >suitable and more efficent for binary computers. This is in addition >to the argument of easier serial addition and multiplication that was mentioned >in the article (though the latter is balanced, to some extent, by serial >comparison and division). > >The main argument left against the LSBians is the more readable MSBian >dump format. I think that in the modern days of optimizing compilers and >symbolic debuggers, dumps are almost an extinct species, and please >let them stay that way. > >I don't have any illusions. I don't expect Motorola to change their byte order >after reading my article. I don't even expect users to prefer LSBian >machines just for the sake of beauty and consistency. >But I do hope that some day the LSBian method will prevail (or, maybe, >someone will convince me of the superiority of the MSBian method...). > Unfortuntately that won't happen either -- the point I am trying to make is that for computational purposes, they byte-ordering question is moot. When you introduce the paradign of typed memory locations and type conversion instructions, the two systems become computationally equivalent. > >Uri Postavsky (utcs!syntron!orcisi!urip) > > (currently with O.R.C Toronto, > formerly with National Semiconductor Tel Aviv). -- Marc Mengel ...!ihnp4!cuuxb!mwm
amos@instable.UUCP (Amos Shapir) (01/11/87)
When I was working on CCI's 6/32, which is basically a vax-like architecture turned MSB-ian, the problem that Uri mentioned (partial read/write to registers) was hard to resolve. The result: on CCI 6/32, a register is always long; that requires sign-extension, but that doesn't take more time than a 'movb'. -- Amos Shapir National Semiconductor (Israel) 6 Maskit st. P.O.B. 3007, Herzlia 46104, Israel (011-972) 52-522261 amos%nsta@nsc 34.48'E 32.10'N
mangler@cit-vax.Caltech.Edu (System Mangler) (01/12/87)
The advantage of little-endian is that it allows type punning,
giving the optimizer a little something extra to work with.
The advantage of big-endian is that it disallows type punning,
making it easy to catch non-portable programming practices.
Don Speck speck@vlsi.caltech.edu {seismo,rutgers,ames}!cit-vax!speckbraun@drivax.UUCP (Karl T. Braun (kral)) (01/12/87)
In article <760@orcisi.UUCP> urip@orcisi.UUCP writes:
- I think that in the modern days of optimizing compilers and
- symbolic debuggers, dumps are almost an extinct species,...
- :
- :
- I don't have any illusions.
'nuf said.
--
kral 408/647-6112 ...!{amdahl,ihnp4}!drivax!braun
"Who is Number One?" "You are, Number Six!"keithe@tekgvs.UUCP (Keith Ericson) (01/12/87)
Who stinkin cares? As you stated in the lead in to your article, you're too late. There's Motorola's way and there's Intel's way. Your way, except that it resembles one of the above, is irrelevant.
radford@calgary.UUCP (Radford Neal) (01/14/87)
In article <1011@cuuxb.UUCP>, mwm@cuuxb.UUCP (Marc W. Mengel) writes: > ... The point I am trying to make > is that for computational purposes, they byte-ordering question is > moot. When you introduce the paradign of typed memory locations and > type conversion instructions, the two systems become computationally > equivalent. Not quite. Consider the following C code: int i; char c; void proc(x) char *x; { ... access to *x; ... } ... c = 'a'; proc(&c); i = 'a'; proc(&i); The two calls to 'proc' both deliver parameters for which *x is 'a' on a little-endian machine, but they don't on a big-endian machine. The litte- endian method thus allows a certain flexibility in typing that the big-endian method doesn't. This is NOT just a notational matter. I do not recommend use of this technique in C code, due to the obvious portability problems. But if little-endian memory were entirely standard it might be a usefull technique, though really you want a more general run-time typing scheme if you want to do this sort of thing. Radford Neal The University of Calgary
bjorn@alberta.UUCP (Bjorn R. Bjornsson) (01/14/87)
In article <753@vaxb.calgary.UUCP>, radford@calgary.UUCP (Radford Neal) writes: > The two calls to 'proc' both deliver parameters for which *x is 'a' on a > little-endian machine, but they don't on a big-endian machine. The litte- > endian method thus allows a certain flexibility in typing that the > big-endian method doesn't. This is NOT just a notational matter. Yes, this is what I call a subset property. Of course Cohen because of his bias never bothered to document this in his supposed plea for peace. This property was exhibited by all the usual data types on a VAX until G and H format floating point came into general use. Cohen focused on the fact that PDP-11/VAX floating point data rep- resentations were not strictly little endian. He was right of course but I think that the subset property is worth mentioning. If you expect an F float by reference in a procedure, it's quite alright for the caller to pass you a D float, what gets lopped off is the least significant (substitute interesting for significant when talking about integers). This subset property is lost in a purely little endian machine, such as the *86 from Intel. What you get there is pure garbage if a caller isn't careful to pass what's expected. But then a language that provides a reasonable facsimile of IEEE floating point arithmetic on a VAX has to forego the subset property, sacrificing the equal width exponents of F and D, in favor of the greater exponent range of G format floating point for double precision implementation. So in the final analysis enter one more alternative into the holy war: The location invariant subset property. When my buss pass runs out, should I run out after it, should I pass, or just buzz? Bjorn R. Bjornsson alberta!bjorn
wsr@lmi-angel.UUCP (Wolfgang Rupprecht) (01/14/87)
In article <> mwm@cuuxb.UUCP (Marc W. Mengel) writes: > The bit notation is strictly notational, and has no bearing on > the operation of the cpu. One could go entirely through any > MC68000 book and replace the bit-numbers appropriately throughout. > > Bit notation (what way you number which bits) has no relation > to byte ordering. I could number my bits: > 13579BDF2468ACE > 000000000000001 > to represent the number 1 if I so chose. Saying that byte ordering > that proceeds in the opposite direction to bit ordering is > some how "inconsistent" is part of your argument, I would maintain > that it is moot. Unfortunately thats not the case. Look at the BSET, BCLR, BTST (bit set, clear and test) instructions. If you do a: BSET.L d0, somelocation with #31 in d0, you have set the MSB (byte 0!) of the long-word. This is *LOW* endian. -- Wolfgang Rupprecht {harvard|decvax!cca|mit-eddie}!lmi-angel!wsr
joel@gould9.UUCP (Joel West) (01/16/87)
The 68000 is big-endian, as is the 68020.
Recently I saw the suggestion that the 68008 is little-endian,
except when fetching opcodes. Could this be true?
If so, does anyone have any idea how many changes would be required
to programs and an OS to make them work on both processors? It
boggles my mind...
--
Joel West MCI Mail: 282-8879
Western Software Technology, POB 2733, Vista, CA 92083
{cbosgd, ihnp4, pyramid, sdcsvax, ucla-cs} !gould9!joel
joel%gould9.uucp@NOSC.ARPAjbn@glacier.STANFORD.EDU (John B. Nagle) (01/17/87)
big-endian, but TP4/MAP is little-endian.
Incidentally, there are some fields in X.25 control frames where the
BITS are in reverse order, for obscure historical reasons.
John Nagleradford@calgary.UUCP (01/17/87)
In article <980@gould9.UUCP>, joel@gould9.UUCP (Joel West) writes: > The 68000 is big-endian, as is the 68020. > > Recently I saw the suggestion that the 68008 is little-endian, > except when fetching opcodes. Could this be true? No, it couldn't be true. A more ridiculous design decision would be hard to imagine. Come to think of it, that may not be all that strong an argument :-) Anyway, I've actually used both 68000 and 68008 processors, and can assure you that they are pretty much compatible. According to the documentation, they even went so far as to have the 68008 trap word accesses at an odd address (I didn't actually try it). Personally, I think this was going too far, especially as (I am given to understand) the 68020 doesn't. (I know, I know, the 68008 came earlier...) Radford Neal The University of Calgary
papowell@umn-cs.UUCP (Patrick Powell) (01/18/87)
In order to spare the innocent, I will briefly note:
mumble proc(x)
char *x;
{ .... }
int i;
char c;
(void) proc(&c); <--O.K.
(void) proc(&i); <--SSSSSSSSSS BOOOOOO
Since when do you assume that a pointer to int has the same FORM
as a pointer to char? Sigh...
I think that the originator of the idea has to work on a word based machine
for his sins.
Patrick ("Two days programming in FORTRAN IV on a IBM 7090 or
50 lashes" "I'll take the lashes!!!") Powell
--
Patrick Powell, Dept. Computer Science, 136 Lind Hall, 207 Church St. SE,
University of Minnesota, Minneapolis, MN 55455 (612)625-3543/625-4002socha@drivax.UUCP (01/23/87)
in reply to: radford@calgary.UUCP (Radford Neal) > In article <980@gould9.UUCP>, joel@gould9.UUCP (Joel West) writes: > > The 68000 is big-endian, as is the 68020. > > > > Recently I saw the suggestion that the 68008 is little-endian, > > except when fetching opcodes. Could this be true? > Anyway, I've actually used both 68000 and 68008 processors, and can assure > you that they are pretty much compatible. According to the documentation, ^^^^^^^^^^^ > Radford Neal The University of Calgary Actually, the 68008 is internally EXACTLY a 68000 with the exception of an interface to an 8 bit bus. i.e. the ALU, microcode, registers all no change! Just whenever the 68000 wants to do a 16 bit read, there are two memory cycles to get the LSB and MSB at their correct 68000 addresses. ---- -- UUCP:...!amdahl!drivax!socha WAT Iron'75 "Everything should be made as simple as possible but not simpler." A. Einstein