campbell@sauron.UUCP (02/10/87)
>[Replying to John Mashey, address given below] >-- >-john mashey DISCLAIMER: <generic disclaimer, I speak for me only, etc> >UUCP: {decvax,ucbvax,ihnp4}!decwrl!mips!mash, DDD: 408-720-1700, x253 >USPS: MIPS Computer Systems, 930 E. Arques, Sunnyvale, CA 94086 Thanks for the reply and example. I guess my problem with your analysis is your assumption that Z < X < Y. Since the hardware designer has the option of not burst filling the cache, it is possible that low-cost machines can be designed (in which there is no external cache and no burst filling) in which Y is equivalent to X. Therefore your condition X < M * Y (don't use the cache) becomes 1 < M and the "don't use cache" condition always holds false. I agree with your bottom line; high miss-rate caches can be dangerous if the miss penalty of the cache exceeds the access time of the main store. If the hardware designer of a particular machine using the MC68030 were to design no external cache then the scenarios which you mention are quite plausible. However, it seems to me that the same hardware designer, knowing that the miss ratio of a 256-byte D-cache would be high (a 50% hit ratio seems generous), would not assert the cache burst acknowledge signal (CBACK). Thus the miss penalty would be reduced from 4X (or 1.y to 3.z, depending upon the use of nybble mode memory, SCRAM, etc.) to 1X, where X is the access time of the main store. Since X is the best case access time without the cache, it would make no sense to turn it off. This was my original point -- however, your posting made me realize the enormity of designing for all of the other cases. Since the cache fill policy of the MC68030 is to try to burst fill a four longword line only if all the valid bits of that line are clear and CBACK is asserted the mathematical model must take account of the line hit and miss rate as well as the D-cache miss and hit rate. On the surface it would appear that burst mode will not occur very often since at least one entry per line will usually be valid (assuming relatively infrequent cache flushes). Thus the miss penalty will be much closer to 1 than to 4 and burst mode (4X) will have little effect on the model even if the hardware designer chose to support it. Like you, I'd be very interested in seeing some simulation data for this cache. -- Mark Campbell {}!ncsu!ncrcae!sauron!campbell