robinson@renoir.Berkeley.EDU (Michael Robinson) (06/28/87)
The Signetics S68000 Users Guide (which is just a photo-reduction of
the Motorola manual) shows the cycle timings to shift a word in a register
as 6+2n (where n is the number of bits to shift), but gives the cycle
timing to shift a word in memory as 8 plus effective address overhead.
Is this a misprint? If not, why is the time to shift a register a
function of n, but the time to shift memory a constant?
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Mike Robinson USENET: ucbvax!ernie!robinson
ARPA: robinson@ernie.berkeley.edugnu@hoptoad.uucp (John Gilmore) (06/28/87)
robinson@renoir.Berkeley.EDU (Michael Robinson) wrote: > why is the time to shift a register a > function of n, but the time to shift memory a constant? Because the 68000 (and 68020) can only shift a memory location by a single bit. It uses the "X" bit for carrying the shifted bit between words, e.g. if you are shifting a 256-bit string, you can do it with a dbra loop over a roxl instruction, but only one bit at a time. Shifting long strings by multiple bits requires more complicated logic, e.g. a funnel shifter rather than a barrel shifter, and a register to hold the intermediate result as it propagates along the string. Motorola didn't get that fancy. -- {dasys1,ncoast,well,sun,ihnp4}!hoptoad!gnu gnu@ingres.berkeley.edu Alt.all: the alternative radio of the Usenet. Contributions welcome - post 'em
nerd@percival.UUCP (Michael Galassi) (06/28/87)
In article <19497@ucbvax.BERKELEY.EDU> robinson@renoir.Berkeley.EDU (Michael Robinson) writes: >The Signetics S68000 Users Guide (which is just a photo-reduction of >the Motorola manual) shows the cycle timings to shift a word in a register >as 6+2n (where n is the number of bits to shift), but gives the cycle >timing to shift a word in memory as 8 plus effective address overhead. >Is this a misprint? If not, why is the time to shift a register a >function of n, but the time to shift memory a constant? There are three forms of the shift operation (logical or arithmetic alike), ASn Dx,Dy | LSn Dx,Dy ASn #x,Dy | LSn #x,Dy ASn <ea> | LSn <ea> The last form will only shift one bit at a time therefore the only uncertainty is how long it will figure out what <ea> realy means (i.e. (a0) will be faster than 6(a0,d1)). The first two forms the shift can do multiple bits in one instruction but the hardware can only shift one bit on every other clock so we get to wait around for this. The rotate instructions work the same way. -michael -- If my employer knew my opinions he would probably look for another engineer. Michael Galassi, Frye Electronics, Tigard, OR ..!{decvax,ucbvax,ihnp4,seismo}!tektronix!reed!percival!nerd
jfh@killer.UUCP (John Haugh) (06/29/87)
In article <19497@ucbvax.BERKELEY.EDU>, robinson@renoir.Berkeley.EDU (Michael Robinson) writes: > The Signetics S68000 Users Guide (which is just a photo-reduction of > the Motorola manual) shows the cycle timings to shift a word in a register > as 6+2n (where n is the number of bits to shift), but gives the cycle > timing to shift a word in memory as 8 plus effective address overhead. > > Is this a misprint? If not, why is the time to shift a register a > function of n, but the time to shift memory a constant? The memory shift operations are single bit shifts only. The register variety can shift more than one at a time, so it takes longer (unless you have a really neat barrel shifter.) That answer this question? - John.