chi@tybalt.caltech.edu (Curt Hagenlocher) (08/28/87)
I understand that the 68030 has a subset of the 68851 instructions on the chip. Will the 68030 work with the 68851? Or is the subset enough to implement all the necessary paging functions? If not, will Motorola be releasing an (updated) version of the 68851 to work with 68030? I read the other day (I can't remember offhand in which journal) an item concerning math chips, and it appears that, although the 68881 has more functions than the 80387, it's takes 125 - 150% as long to complete some tasks. Will Motorola be releasing a new math chip with the '030? I would appreciate it it someone could send me the answers to my queries as it could affect a personal project I'm working on. Or maybe it would be worthwhile to post the replies: I'm sure that other people would like to know the answers as much as I would. Thank you. ++++++++++++++++++++++++++++++++++++++++++++ Curt Hagenlocher chi@tybalt.caltech.edu chi@citromeo.caltech.bitnet seismo!cit-vax!tybalt.caltech.edu!chi
alan@pdn.UUCP (Alan Lovejoy) (08/31/87)
In article <3792@cit-vax.Caltech.Edu> chi@tybalt.caltech.edu (Curt Hagenlocher) writes: >I understand that the 68030 has a subset of the 68851 instructions on >the chip. Will the 68030 work with the 68851? Or is the subset enough >to implement all the necessary paging functions? If not, will Motorola >be releasing an (updated) version of the 68851 to work with 68030? >tasks. Will Motorola be releasing a new math chip with the '030? The 68851 functionality that is missing from the 68030 mostly concerns the debugging facilities (i.e., the breakpoint registers). The memory management code in an operating system should not be affected by this, debuggers definitely will be. I *believe* that the native MMU functionality of the '030 can be disabled, allowing external devices to take over this function, but you should probably verify that with Motorola. Motorola has announced the 68882 FPU, which has been designed to work with either the '020 or the '030. The 68882 will take more advantage of the parallelism possible with a CPU/FPU system, and will also allow multiple FPU's to work on the same problem in parallel. In fact, that is Motorola's 'graphics coprocessor' strategy: a board with multiple 68882's working in parallel. --alan@pdn