gnu@hoptoad.uucp (John Gilmore) (10/22/87)
I just looked over a preliminary data sheet for the 68070 tonight.
It's basically a 10 MHz 68000 with a crazed 'segment based' mmu, UART,
timers, DMA channel, kitchen sink, etc all on a CMOS chip in a small
plastic chip carrier. It also has 68010 style bus errors (virtual memory)
and a CLR instruction that doesn't read its target. Its memory bus
is the standard 68000/68010 4 clock cycle, with 24 address bits, 16 data
bits, but no function codes. Interrupts are simpler but well designed.
I hear there are a bunch of second sources lined up.
However, for some reason just about EVERY instruction runs from 1 to 15
cycles SLOWER than the 68000! All the simple instructions run in 7
cycles instead of 4; long math to registers 1 cycle slower, to memory 3
cycles slower; branches are 2 to 5 cycles slower; JSR 9 cycles slower.
Base/displacement addressing (e.g. stack references) is 3 cycles slower.
Even worse, MOVEM takes 7 cycles per short or 11 per long, meaning you
can't do block moves at memory bandwidth. And DBRA is 7 cycles slower
when it loops. All of the above is with the MMU turned off; if you turn
it on, you lose a wait state on each memory reference, too.
In fairness, byte, word, and long operations in registers now all take
the same amount of time, though all these times are still slower than
the 68000; and a very few instructions are faster (RTS).
Watching this puppy on a scope is going to show a lot of "dead time" on
the memory bus, like the 68000 never had. They have clearly redesigned
the guts of the CPU; it looks almost like they are incrementing the PC
with the ALU. Does anybody know why? I thought Signetics was licensed
to produce the 68000; why didn't they just use the old one? It wasn't
a 68020 but it was at least as fast as a 68000...
--
{dasys1,ncoast,well,sun,ihnp4}!hoptoad!gnu gnu@toad.compwv@fluke.UUCP (10/28/87)
In article <3240@hoptoad.uucp> gnu@hoptoad.uucp (John Gilmore) writes: >I just looked over a preliminary data sheet for the 68070 tonight. >It's basically a 10 MHz 68000 with a crazed 'segment based' mmu, UART, >timers, DMA channel, kitchen sink, etc all on a CMOS chip in a small >plastic chip carrier. ... <pruned> > >However, for some reason just about EVERY instruction runs from 1 to 15 >cycles SLOWER than the 68000! All the simple instructions run in 7 >cycles instead of 4; .... <pruned> I think that you missed one very important fact, John: the 68070 uses a 2X clock scheme: Where a 68000 counts T states of a 10 MHz clock the 68070 counts it's states off a 20 MHz clock BUT uses a 10 MHz bus clock. Soooo, the 68070 actually runs FASTER than a 68000 of equivalent BUS speed. > <pruned> ... I thought Signetics was licensed >to produce the 68000; why didn't they just use the old one? It wasn't >a 68020 but it was at least as fast as a 68000... CMOS. See your the first paragraph of your message. If you want to get more information from the horses mouth, so to speak, Michael Gordan Weaver (weaver@prls.UUCP) of Signetics Microprocessor Division and Junien Labrousse (junien@prls.UUCP) of Philips Research Labs have both posted info on the 68070 in this forum last May. (Junien also claims to be one of the architects.) -- Pat Vilbrandt John Fluke Mfg. Co., Inc. Everett, Washington USA UUCP: { ihnp4!uw-beaver, ucbvax!lbl-csam, allegra, ssc-vax }!fluke!pwv domain style address: pwv@tc.fluke.COM ARPA: fluke!pwv@uw-beaver.ARPA